AT25DF321A Datasheet PDF - ATMEL Corporation
| Part Number | AT25DF321A | |
| Description | 32-Megabit 2.7-volt MinimumSPI Serial Flash Memory | |
| Manufacturers | ATMEL Corporation | |
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Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS® Operation
– Supports Dual-Input Program and Dual-Output Read
• Very High Operating Frequencies
– 100 MHz for RapidS
– 85 MHz for SPI
– Clock-to-Output (tV) of 5 ns Maximum
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature
– 64 Sectors of 64-Kbytes Each
• Hardware Controlled Locking of Protected Sectors via WP Pin
• Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
• 128-Byte Programmable OTP Security Register
• Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
• Fast Program and Erase Times
– 1.0 ms Typical Page Program (256 Bytes) Time
– 50 ms Typical 4-Kbyte Block Erase Time
– 250 ms Typical 32-Kbyte Block Erase Time
– 400 ms Typical 64-Kbyte Block Erase Time
• Program and Erase Suspend/Resume
• Automatic Checking and Reporting of Erase/Program Failures
• Software Controlled Reset
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 5 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
32-Megabit
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25DF321A
Preliminary
1. Description
The AT25DF321A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DF321A, with its erase granularity as small as
4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
3686C–DFLASH–12/08
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3. Block Diagram
Figure 3-1. Block Diagram
CS
SCK
SI (SIO)
SO (SOI)
WP
HOLD
INTERFACE
CONTROL
AND
LOGIC
AT25DF321A [Preliminary]
CONTROL AND
PROTECTION LOGIC
Y-DECODER
X-DECODER
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
Y-GATING
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF321A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated regions. The
Memory Architecture Diagram illustrates the breakdown of each erase level as well as the
breakdown of each physical sector.
3686C–DFLASH–12/08
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AT25DF321A electronic component. |
| Information | Total 58 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AT25DF321A.PDF Datasheet ] | |
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