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What is AT25DF011?

This electronic component, produced by the manufacturer "Adesto", performs the same function as "SPI Serial Flash Memory".


AT25DF011 Datasheet PDF - Adesto

Part Number AT25DF011
Description SPI Serial Flash Memory
Manufacturers Adesto 
Logo Adesto Logo 


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Total 30 Pages



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AT25DF011
1-Mbit, 1.65V Minimum
SPI Serial Flash Memory with Dual-I/O Support
Features
PRELIMINARY DATASHEET
Single 1.65V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
85MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
400ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
200nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
5mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Temperature Range:-10°C to +85°C (1.65V to 3.6V), -40°C to +85° (1.7V to 3.6V)
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
8-lead TSSOP Package
DS-25DF011–032A–4/2014

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AT25DF011 equivalent
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF011 can be erased in three levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
Figure 4-1. Memory Architecture Diagram
Block Erase Detail
32KB
4KB
Block Erase
Block Erase
(52h Command) (20h Command)
Block Address
Range
32KB
32KB
32KB
32KB
4KB 01FFFFh – 01F000h
4KB 01EFFFh – 01E000h
4KB 01DFFFh – 01D000h
4KB 01CFFFh – 01C000h
4KB 01BFFFh – 01B000h
4KB 01AFFFh – 01A000h
4KB 019FFFh – 019000h
4KB 018FFFh – 018000h
4KB 017FFFh – 017000h
4KB 016FFFh – 016000h
4KB 015FFFh – 015000h
4KB 014FFFh – 014000h
4KB 013FFFh – 013000h
4KB 012FFFh – 012000h
4KB 011FFFh – 011000h
4KB 010FFFh – 010000h
4KB 00FFFFh – 00F000h
4KB 00EFFFh – 00E000h
4KB 00DFFFh – 00D000h
4KB 00CFFFh – 00C000h
4KB 00BFFFh – 00B000h
4KB 00AFFFh – 00A000h
4KB 009FFFh – 009000h
4KB 008FFFh – 008000h
4KB 007FFFh – 007000h
4KB 006FFFh – 006000h
4KB 005FFFh – 005000h
4KB 004FFFh – 004000h
4KB 003FFFh – 003000h
4KB 002FFFh – 002000h
4KB 001FFFh – 001000h
4KB 000FFFh – 000000h
Page Program Detail
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
Page Address
Range
01FFFFh – 01FF00h
01FEFFh – 01FE00h
01FDFFh – 01FD00h
01FCFFh – 01FC00h
01FBFFh – 01FB00h
01FAFFh – 01FA00h
01F9FFh – 01F900h
01F8FFh – 01F800h
01F7FFh – 01F700h
01F6FFh – 01F600h
01F5FFh – 01F500h
01F4FFh – 01F400h
01F3FFh – 01F300h
01F2FFh – 01F200h
01F1FFh – 01F100h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
000EFFh – 000E00h
000DFFh – 000D00h
000CFFh – 000C00h
000BFFh – 000B00h
000AFFh – 000A00h
0009FFh – 000900h
0008FFh – 000800h
0007FFh – 000700h
0006FFh – 000600h
0005FFh – 000500h
0004FFh – 000400h
0003FFh – 000300h
0002FFh – 000200h
0001FFh – 000100h
0000FFh – 000000h
5. Device Operation
The AT25DF011 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25DF011 via the SPI bus which is comprised of four signal lines: Chip
Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF011
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
AT25DF011
DS-25DF011–032A–4/2014
5


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On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AT25DF011 electronic component.


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AT25DF011The function is SPI Serial Flash Memory. AdestoAdesto

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