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PDF HCF4099B Data sheet ( Hoja de datos )
| Número de pieza | HCF4099B | |
| Descripción | 8-BIT ADDRESSABLE LATCH | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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HCC/HCF4099B
. SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
. STORAGE REGISTER CAPABILITY - MASTER
CLEAR
. CAN FUNCTION AS DEMULTIPLEXER
. STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD N°. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
8-BIT ADDRESSABLE LATCH
EY
Plastic Package
F
Ceramic Frit Seal Package
M1
Micro Package
C1
Plastic Chip Carrier
ORDER CODES :
HCC4099BF
HCF4099BM1
HCF4099BEY HCF4099BC1
PIN CONNECTIONS
DESCRIPTION
The HCC4099B (extended temperature range) and
HCF4099B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead dual
in-line plastic or ceramic package and plastic micro
package. The HCC/HCF4099B 8-bit addressable
latch is a serial-input, parallel-output storage register
that can perform a variety of functions. Data are in-
putted to a particular bit in the latch when that bit is
addressed (by means of inputs A0, A1, A2) and
when WRITE DISABLE is at a low level. When
WRITE DISABLE is high, data entry is inhibited ;
however, all 8 outputs can be continuously read in-
dependent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all
bits to a logic ”0” level when RESET and WRITE
DISABLE are at a high level. When RESET is at a
high level, and WRITE DISABLE is at a low level, the
latch acts as a 1-of-8 demultiplexer ; the bit that is
addressed has an active output which follows the
data input, while all unaddressed bits are held to a
logic ”0” level.
September 1988
1/14
1 page  
HCC/HCF4099B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200kΩ,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall times = 20ns)
Symbol
Parameter
t PL H, tP HL Propagation
Delay Time
Data to Output
Test Conditions
(see master timing
diagram)
(1)
Value
V D D (V) Min. Typ. Max.
5 200 400
10 75 150
Write Disable to
Output
(2)
15 50 100
5 200 400
10 80 160
15 60 120
Address to
Output
5 225 450
(9) 10 100 200
15 75 150
tPHL Propagation Reset to Output
Delay Time
(3)
5 175 350
10 80 160
15 65 130
t THL, tT L H Transition
Time
Any Output
5 100 200
10 50 100
15 40 80
tW Pulse Width Data
5 200 100
(4) 10 100 50
15 80 40
Address
5 400 200
(8) 10 200 100
Reset
15 125 65
5 150 75
(5) 10 75 40
15 50 25
t s e t u p Setup Time
Data to Write
5 100 50
Disable
(6) 10 50 25
15 35 20
t h o ld Hold Time
Data to Write
5 150 75
Disable
(7) 10 75 40
15 50 25
Unit
ns
ns
ns
ns
ns
5/14
5 Page 
DIM.
A
B
D
E
e3
F
G
H
L
M
N
P
Q
HCC/HCF4099B
Ceramic DIP16/1 MECHANICAL DATA
MIN.
0.38
2.29
0.4
1.17
0.22
0.51
7.8
mm
TYP.
3.3
17.78
MAX.
20
7
2.79
0.55
1.52
0.31
1.27
10.3
8.05
5.08
MIN.
0.015
0.090
0.016
0.046
0.009
0.020
0.307
inch
TYP.
0.130
0.700
MAX.
0.787
0.276
0.110
0.022
0.060
0.012
0.050
0.406
0.317
0.200
P053D
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HCF4099B.PDF ] | |
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