|
|
PDF GW3887AIKZ-TK Data sheet ( Hoja de datos )
| Número de pieza | GW3887AIKZ-TK | |
| Descripción | Wireless LAN Integrated Medium Access Controller | |
| Fabricantes | Conexant | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de GW3887AIKZ-TK (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
GW3887A
Wireless LAN Integrated Medium Access Controller with
Baseband Processor
The Conexant GW3887A Wireless LAN Integrated Media Access Controller
with Baseband Processor is part of both the PRISM GT™ single band and
PRISM WWR™ dual band radio chip sets. The GW3887A directly interfaces
with Conexant’s ISL3686B Single Band Direct Conversion Transceiver.
Adding Conexant’s ISL3084 5GHz VCO and ISL3980 Power Amp completes
an end-to-end WLAN chip set solution compliant with 802.11b/g standards.
Additionally, the GW3887A directly interfaces with Conexant’s ISL3692 Dual
Band Direct Conversion Transceiver. Adding Conexant’s ISL3092 11GHz
VCO and ISL3992 Dual Band Power Amp completes an end-to-end WLAN
chip set solution compliant with 802.11a/b/g/h/i/j standards. The 802.11
protocol is implemented in firmware supporting custom WLAN solutions.
The GW3887A improvements over the GW3887 include the addition of an
internal 48MHz oscillator, which eliminates several external components
from the radio design.
Software implements the full IEEE 802.11 Wireless LAN MAC protocol. It
supports BSS and IBSS operation under DCF, and operation under the
optional Point Coordination Function (PCF). Active scanning is performed
autonomously once initiated by host command. Host interface command
and status handshakes allow concurrent operations from multi-threaded I/
O drivers.
Orthogonal Frequency Division Multiplexing (OFDM) of 52 sub-carriers
modulated with BPSK, QPSK, 16QAM or 64QAM and a variety of
convolutional coding rates provides 8 selectable data rates at 2.4GHz and
5GHz. Differential phase shift keying modulation schemes, DBPSK and
DQPSK with data scrambling capability along with Complementary Code
Keying provide an additional 4 selectable data rates at 2.4GHz.
Built-in flexibility allows the GW3887A to be configured for a range of
applications. The MAC is based on the ARM 946E processor core that
offers a wide variety of code development support tools.
The GW3887A is housed in a thin plastic BGA package suitable for USB
2.0 Wireless LAN small form factor circuit card applications.
Features
• Firmware implements the full IEEE
802.11a/b/g/h/i/j Wireless LAN MAC
protocols
• Internal WEP Engine allows 64 or 128 bit
Encryption
• AES Hardware Accelerator
• Start-up modes allow the USB vendor and
device ID to be initialized from a small
external serial EEPROM. This allows
firmware to be downloaded from the host.
• On-chip SRAM memory
• A low frequency crystal oscillator can
maintain time, which allows the high
frequency clock source to be powered off
during sleep mode.
• Firmware controlled antenna diversity
• Data Rates: 1, 2, 5.5, 6, 9, 11, 12, 18, 24,
36, 48, & 54Mbps
• Modulation: OFDM with BPSK, QPSK,
16QAM, 64QAM; DBPSK; DQPSK and
CCK
• Convolutional coding and interleaving on
all OFDM rates
• Targeted for OFDM Multipath Delay
Spreads >800ns for 6Mbps, and >100ns
for 54Mbps
• Targeted for CCK Multipath Delay
Spreads >90ns at 11Mbps, >200ns at
5.5Mbps and >360ns at 1 and 2Mbps
• Direct interface with the ISL3692 and
ISL3686 Direct Conversion transceiver
• USB 2.0 Wireless LAN Adapters
A/D
BB
PROCESSOR
MAC
USB
2.0
Interface
D/A
GW3887A
SRAM
Figure 1: Simplified Block Diagram
Preliminary Data Sheet
November 12, 2004
Conexant Systems, Inc.
Proprietary - Use Pursuant to NDA
DO-406971-DS
Issue 2
1 page  
November 12, 2004
GW3887A Data Sheet
Table 1: GW3887A Signal Descriptions (Sheet 4 of 5)
Pin Name
FSADpabias
GP1-6
LFXTALOUT
LFXTALIN
GNDD
GNDA1
FSADoff
VDDA3
GNDA3
GNDD
FSADiq
GNDA4
RX_IFagc_N
FSADtx
VSUB2
LOOP44
GNDAPLL
GP1-4
GP1-10
VDDA1
VDDD0
VDDA2
VREF
Iref
VDDA4
ioVDDD
Qout_P
TX_IQ_det
COMPrx
GNDA5
VDDD1
NC
GNDAPLL
GP2-14
coreVDDD
VSUB1
NC
COMPioff
Iin_N
Qin_P
Iout_P
GP1-1
Qout_N
PA_det
RX_IFagc_P
FSADrx
BGA Ball
Assignment
n16
n2
n3
n4
n5
n6
n7
n8
n9
p1
p10
p11
p12
p13
p14
p15
p16
p2
p3
p4
p5
p6
p7
p8
p9
r1
r10
r11
r12
r13
r14
r15
r16
r2
r3
r4
r5
r6
r7
r8
r9
t1
t10
t11
t12
t13
Pad Type
analog
Bidir
Xtal output
Xtal input
supply
analog
analog
analog
analog
supply
analog
analog
analog
analog
analog
analog
analog
Bidir
Bidir
analog
analog
analog
analog
analog
analog
supply
analog
analog
analog
analog
analog
none
analog
Bidir
supply
analog
none
analog
analog
analog
analog
Bidir
analog
analog
analog
analog
Pin I/O
TYPE
none
down
-------
--------
none
none
none
none
none
none
none
none
none
none
none
none
none
down
down
none
none
none
none
none
none
none
none
none
none
none
none
none
none
up
none
none
none
none
none
none
none
down
none
none
none
none
Description
Full scale adjust resistor for PA bias DAC
SYNTHDAT
Low frequency (32kHz) crystal pad
Low frequency (32kHz) crystal pad
Digital IO and core ground
Analog ground to 12bit DACs
Full scale adjust resistor for 12bit DACS
Analog supply to ADCs
Analog ground to ADCs
Digital IO and core ground
Full scale adjust resistor for Tx DACs
Analog ground for Tx DACs
Iout- for BB Rx AGC DAC (BB_AGC-)
Full scale adjust resistor for Tx AGC DAC
Substrate pad (ground)
Loop compensation network for 44MHz output PLL
PLL ground
SYNTH_LE
TRSW
Analog supply to offset DACs (2.85V)
Offset DACs digital supply (2.85V)
Analog supply to offset DACs
Band gap voltage reference input
Current reference resistor
Analog supply to Tx DACs
Digital IO supply (3.3V)
Iout+ for Q Tx DAC (TXQ+)
When CalModeEN=1 this is selected as input to TXDET ADC
Compensation cap for Rx AGC DAC
Analog ground for RX and TX AGC DAC
Digital supply for DACs other than offset (2.85V)
No connect, no pad
PLL ground
LED0
Digital core supply(1.8V)
Substrate tie (ground)
No connect, no pad
Comp pin for offset DACs
Input signal for I Rx ADC (RXI-)
Input signal + for Q Rx ADC (RXQ+)
Iout+ for I Tx DAC (TXI+)
HB_LB (High band/ Low Band) high band when
Iout- for Q Tx DAC (TXQ-)
When CalModeEN=0 this is select as input to TXDET ADC
Iout+ for BB Rx AGC DAC (BB_AGC+)
Full scale adjust resistor for Rx AGC DAC
DO-406971-DS
Issue 2
Conexant Systems, Inc.
Proprietary - Use Pursuant to NDA
5
5 Page 
November 12, 2004
GW3887A Data Sheet
13 Outline Diagrams
A1
CORNER
A1
CORNER I.D.
A
D
E
TOP VIEW
B
0.15
0.006
MC
A
B
0.08
0.003
MC
D1
A1
CORNER
b
S
A
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A1
CORNER I.D.
A
B
C
D
E
F
G
H E1
J
K
L
M
N
P
R
T
A1
A2
S
A
BOTTOM VIEW
e
ALL ROWS AND COLUMNS
bbb C
C
A
SEATING PLANE
SIDE VIEW
aaa C
Table 5: V192.14x14B 192 Ball Plastic Ball Grid
Array Package
Symbol
Inches
Min Max
Millimeters
Min Max
Notes
A
A1
A2
b
D/E
D1/E1
N
e
MD/ME
bbb
aaa
- 0.047
0.010 0.014
0.026 0.035
0.014 0.018
0.547 0.555
0.468 0.476
192
0.032 BSC
16 x 16
0.004
0.005
-
0.25
0.67
0.35
13.90
11.90
192
0.80 BSC
16 x 16
0.10
0.12
1.20
0.35
0.90
0.45
14.10
12.10
-
-
-
7
-
-
-
-
3
-
-
NOTES for Figure 6 and Table 5:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. Dimensioning and tolerancing conform to ASME
Y14.5M-1994.
3. “MD” and “ME” are the maximum ball matrix size for
the “D” and “E” dimensions, respectively.
4. “N” is the maximum number of balls for the specific
array size.
5. Primary datum C and seating plane are defined by
the spherical crowns of the contact balls.
6. Dimension “A” includes standoff height “A1”, package
body thickness and lid or cap height “A2”.
7. Dimension “b” is measured at the maximum ball
diameter, parallel to the primary datum C.
8. Pin “A1” is marked on the top and bottom sides
adjacent to A1.
9. “S” is measured with respect to datum’s A and B and
defines the position of the solder balls nearest to
package centerlines. When there is an even number
of balls in the outer row the value is “S” = e/2.
Figure 6: Plastic Ball Grid Array Packages
(BGA)
DO-406971-DS
Issue 2
Conexant Systems, Inc.
Proprietary - Use Pursuant to NDA
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet GW3887AIKZ-TK.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| GW3887AIKZ-TK | Wireless LAN Integrated Medium Access Controller | Conexant |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |