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PDF 70N20 Data sheet ( Hoja de datos )

Número de pieza 70N20
Descripción FDA70N20
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 70N20 Hoja de datos, Descripción, Manual

FDA70N20
N-Channel UniFETTM MOSFET
200 V, 70 A, 35
Features
• RDS(on) = 35 mΩ (Max.) @ VGS = 10 V, ID = 35 A
• Low Gate Charge (Typ. 66 nC)
Low Crss (Typ. 89 pF)
• 100% Avalanche Tested
Applications
• Uninterruptible Power Supply
• AC-DC Power Supply
December 2013
Description
UniFETTM MOSFET is Fairchild Semiconductor’s high voltage
MOSFET family based on planar stripe and DMOS technology.
This MOSFET is tailored to reduce on-state resistance, and to
provide better switching performance and higher avalanche
energy strength. This device family is suitable for switching
power converter applications such as power factor correction
(PFC), flat panel display (FPD) TV power, ATX and electronic
lamp ballasts.
D
G
D
S
TO-3PN
Absolute Maximum Ratings TC = 25°C unless otherwise noted.
Symbol
Parameter
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
(Note 1)
Gate-Source voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation
(TC = 25°C)
- Derate Above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purpose,
1/8” from Case for 5 Seconds
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case, Max.
Thermal Resistance, Case-to-Sink, Typ.
Thermal Resistance, Junction-to-Ambient, Max.
G
S
FDA70N20
200
70
45
280
±30
1742
70
41.7
4.5
417
3.3
-55 to +150
300
FDA70N20
0.3
0.24
40
©2005 Fairchild Semiconductor Corporation
FDA70N20 Rev C1
1
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Unit
°C/W
°C/W
°C/W
www.fairchildsemi.com
http://www.Datasheet4U.com

1 page




70N20 pdf
Same Type
50KΩ as DUT
12V 200nF
300nF
VGS
10V
Qg
VGS
VDS
Qgs Qgd
IG = const.
DUT
Charge
Figure 12. Gate Charge Test Circuit & Waveform
VGS
VDS
VGS
RG
RL
VDD
DUT
VDS
90%
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
Figure 13. Resistive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS
=
--1--
2
L IAS2
BVDSS
--------------------
BVDSS -V DD
BVDSS
IAS
VDD ID (t)
VGS
DUT
VDD
VDS (t)
t p t p Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2005 Fairchild Semiconductor Corporation
FDA70N20 Rev C1
5
www.fairchildsemi.com

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