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PDF ADSP-21469 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21469 | |
| Descripción | SHARC Processor | |
| Fabricantes | Analog Devices | |
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SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM
Up to 450 MHz operating frequency
Qualified for automotive applications, see Automotive Prod-
ucts on Page 70
Code compatible with all other members of the SHARC family
SHARC Processor
ADSP-21469
The ADSP-21469 processor is available with unique audio-
centric peripherals such as the digital applications
interface, DTCP (digital transmission content protection
protocol), serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more.
For complete ordering information, see Ordering Guide on
Page 70
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
PEx
Timer
PEy
FLAGx/IRQx/
TMREXP
JTAG
THERMAL
DIODE
DMD
64-BIT
PMD
64-BIT
PERIPHERAL BUS
CORE PCG
FLAGS C-D
TIMER
1-0
TWI
SPI/B UART
DPI Routing/Pins
DPI Peripherals
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
S
Core Bus
Cross Bar
DMD
64-BIT
PMD 64-BIT
EPD BUS 64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
PERIPHERAL
BUS 32-BIT
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC PDAP/ SPORT
3-0 IDP 7-0
7-0
DAI Routing/Pins
DAI Peripherals
IOD1
32-BIT
FFT DTCP/
FIR MTM
IIR
SPEP BUS
LINK CORE PWM
MLB PORT FLAGS 3-0
1-0
EP
AMI DDR2
CTL
External Port Pin MUX
External
Port
Peripherals
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.326.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com
1 page  
ADSP-21469
S
SIMD Core
DMD/PMD 64
DAG1
16x32
DAG2
16x32
JTAG FLAG TIMER INTERRUPT CACHE
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
PM DATA 48
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
MULTIPLIER SHIFTER ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ALU
SHIFTER MULTIPLIER
MRF
80-BIT
MRB
80-BIT
ASTATx
STYKx
ASTATy
STYKy
MSB
80-BIT
MSF
80-BIT
Figure 2. SHARC Core Block Diagram
other data structures required in digital signal processing, and
are commonly used in digital filters and Fourier transforms.
The two DAGs of the processors contain sufficient registers to
allow the creation of up to 32 circular buffers (16 primary regis-
ter sets, 16 secondary). The DAGs automatically handle address
pointer wraparound, reduce overhead, increase performance,
and simplify implementation. Circular buffers can start and end
at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21469 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the ADSP-21469 supports new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
DDR2 memory. Source modules need to be built using the
VISA option in order to allow code generation tools to create
these more efficient opcodes.
On-Chip Memory
The processors contain 5 Mbits of internal RAM. Each block
can be configured for different combinations of code and data
storage (see Table 4). Each memory block supports single-cycle,
independent accesses by the core processor and I/O processor.
The ADSP-21469 memory architecture, in combination with its
separate on-chip buses, allows two data transfers from the core
and one from the I/O processor in a single cycle.
The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5 Mbits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
Rev. 0 | Page 5 of 72 | June 2010
Free Datasheet http://www.Datasheet4U.com
5 Page 
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21469 pro-
cessors to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor's JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate Emulator Hardware User's Guide.
DEVELOPMENT TOOLS
The ADSP-21469 processor is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21469 processors.
EZ-KIT Lite Evaluation Board
For evaluation of the processors, use the EZ-KIT Lite® board
being developed by Analog Devices. The board comes with on-
chip emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-
circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com-
mands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
ADSP-21469
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite® evaluation plat-
forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++® development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a stand-
alone unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, non-
intrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21469
architecture and functionality. For detailed information on the
ADSP-21469 family core architecture and instruction set, refer
to the SHARC Processor Programming Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
Wikipedia or the Glossary of EE Terms on the Analog Devices
website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Application Signal Chains page in the Circuits from the
LabTM site (http://www.analog.com/signalchains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Rev. 0 | Page 11 of 72 | June 2010
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