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What is STA559BW?

This electronic component, produced by the manufacturer "STMicroelectronics", performs the same function as "2.1 channel high-efficiency digital audio system".


STA559BW Datasheet PDF - STMicroelectronics

Part Number STA559BW
Description 2.1 channel high-efficiency digital audio system
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 


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No Preview Available ! STA559BW datasheet, circuit

STA559BW
5 V, 2 A, 2.1 channel high-efficiency digital audio system
Sound Terminal®
Datasheet - production data
PowerSSO-36
with exposed pad down (EPD)
Features
Wide-range supply voltage, 4.5 V to 16 V
Three power output configurations:
– 2 channels of ternary PWM (2 x 3 W into
4 at 5 V) + PWM output
– 2 channels of ternary PWM (2 x 3 W into
4 at 5 V) + ternary stereo line-out
– 2.1 channels of binary PWM (left, right,
LFE) (2 x 0.7 W + 1 x 3 W into 4 at 5 V)
(2 x 1.4 W + 1 x 6 W into 2 at 5 V)
FFX with 100-dB SNR and dynamic range
Selectable 32- to 192-kHz input sample rates
I²C control with selectable device address
Digital gain/attenuation +48 dB to -80 dB with
0.5-dB/step resolution
Soft volume update
Individual channel and master gain/attenuation
Two independent limiters/compressors
Dynamic range compression or anti-clipping
modes
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel soft/hard mute
Independent channel volume and DSP bypass
2-channel I²S input data interface
Input and output channel mapping
Automatic invalid-input detect Mute
Automatic zero-detect mute
Up to 4 user-programmable biquads/channel
Three coefficients banks for EQ presets storing
with fast recall via I²C interface
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
Selectable high- or low-bandwidth
noise-shaping topologies
Selectable clock input ratio
Thermal overload and short-circuit protection
embedded
Video apps: 576 x fS input mode supported
Table 1. Device summary
Order code
Package
Packaging
STA559BWTR PowerSSO-36 EPD Tape and reel
February 2014
This is information on a product in full production.
DocID18190 Rev 2
1/67
www.st.com
http://www.Datasheet4U.com

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STA559BW equivalent
STA559BW
List of figures
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Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Left and right processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Output configuration for stereo BTL mode (RL = 8  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DocID18190 Rev 2
5/67
67
http://www.Datasheet4U.com


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Part Details

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