PDF 1024-883 Data sheet ( Hoja de datos )

Número de pieza	1024-883
Descripción	1024/883 In-System Programmable High Density PLD
Fabricantes	Lattice
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No Preview Available ! ispLSI ® 1024/883 In-System Programmable High Density PLD Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs — 144 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Fast Random Logic — Security Cell Prevents Unauthorized Copying • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 60 MHz Maximum Operating Frequency — tpd = 20 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested • IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms unctional Block Diagram Functional Block Diagram A0 C7 A1 D Q C6 A2 D Q C5 Logic A3 Array D Q GLB C4 A4 C3 DQ A5 C2 A6 C1 A7 Global Routing Pool (GRP) C0 B0 B1 B2 B3 B4 B5 B6 B7 CLK Output Routing Pool Description 0139-A-isp The ispLSI 1024/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD- 883. This military grade device contains 144 Registers, 48 Universal I/O pins, six Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024/883 features 5-Volt in-system programmability and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1024/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see figure 1). There are a total of 24 GLBs in the ispLSI 1024/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 1024MIL_01 1 http://www.Datasheet4U.com 1 page Specifications ispLSI 1024/883 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 5 COND. #2 DESCRIPTION1 tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 A 1 Data Propagation Delay, 4PT bypass, ORP bypass A 2 Data Propagation Delay, Worst Case Path A 3 Clock Frequency with Internal Feedback3 – 4 Clock Frequency with External Feedback (tsu2 1 + )tco1 – 5 Clock Frequency, Max Toggle 4 – 6 GLB Reg. Setup Time before Clock, 4PT bypass A 7 GLB Reg. Clock to Output Delay, ORP bypass – 8 GLB Reg. Hold Time after Clock, 4 PT bypass – 9 GLB Reg. Setup Time before Clock – 10 GLB Reg. Clock to Output Delay – 11 GLB Reg. Hold Time after Clock A 12 Ext. Reset Pin to Output Delay – 13 Ext. Reset Pulse Duration B 14 Input to Output Enable C 15 Input to Output Disable – 16 Ext. Sync. Clock Pulse Duration, High – 17 Ext. Sync. Clock Pulse Duration, Low – 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) – 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit loadable counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions Section. -60 UNITS MIN. MAX. – 20 ns – 25 ns 60 – MHz 38 – MHz 83 – MHz 9 – ns – 13 ns 0 – ns 13 – ns – 16 ns 0 – ns – 22.5 ns 13 – ns – 24 ns – 24 ns 6 – ns 6 – ns 2.5 – ns 8.5 – ns Table 2-0030-24 mil 5 http://www.Datasheet4U.com 5 Page Pin Configuration ispLSI 1024/883 68-Pin JLCC Pinout Diagram Specifications ispLSI 1024/883 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 IN 5 Y0 VCC GND ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 ispLSI 1024/883 53 18 52 19 Top View 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 IN 3/MODE1 Y1 VCC GND Y2 Y3 IN 2/SCLK1 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 1. Pins have dual function capability. 0123-24-isp/JLCC 11 http://www.Datasheet4U.com 11 Page

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