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PDF 74HC574 Data sheet ( Hoja de datos )
| Número de pieza | 74HC574 | |
| Descripción | Octal 3-State Noninverting D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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74HC574
Octal 3−State Noninverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
The 74HC574 is identical in pinout to the LS574. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
The HC574 is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
• This is a Pb−Free Device
20
1
http://onsemi.com
MARKING
DIAGRAMS
20
TSSOP−20
DT SUFFIX
CASE 948E
1
HC
574
ALYW G
G
HC574 = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1
Publication Order Number:
74HC574/D
http://www.Datasheet4U.com
1 page  
74HC574
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
(V)
Guaranteed Limit
*55 to 25_C v85_C v125_C
Unit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 3 and 6)
2.0 6.0
3.0 15
4.5 30
6.0 35
4.8 4.0 MHz
10 8.0
24 20
28 24
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 3 and 6)
2.0 160 200 240 ns
3.0 105 145 190
4.5 32
40 48
6.0 27
34 41
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0 150 190 225 ns
3.0 100 125 150
4.5 30
38 45
6.0 26
33 38
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0 140
3.0 90
4.5 28
6 0 24
175 210 ns
120 140
35 42
30 36
tTLH,
tTHL
Maximum Output Transition Time, any Output
(Figures 3 and 6)
2.0 60
3.0 27
4.5 12
6.0 10
75 90 ns
32 36
15 18
13 15
Cin Maximum Input Capacitance
Cout Maximum Three−State Output Capacitance, Output in High−Impedance
State
10 10 10 pF
15 15 15 pF
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Enabled Output)*
24 pF
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCC – 55 to 25_C
v 85_C
v 125_C
Figure (V) Min Max Min Max Min Max Unit
tsu Minimum Setup Time, Data to Clock
5 2.0 50 65 75 ns
3.0 40 50 60
4.6 10 13 15
6.0 9.0 11 13
th Minimum Hold Time, Clock to Data
5 2.0 5.0
5.0
5.0
ns
3.0 5.0 5.0 5.0
4.5 5.0 5.0 5.0
6.0 5.0 5.0 5.0
tw Minimum Pulse Width, Clock
3 2.0 75
3.0 60
4.5 15
6.0 13
95 110 ns
80 90
19 22
16 19
tr, tf Maximum Input Rise and Fall Times
3 2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74HC574.PDF ] | |
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