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PDF MX25L25835E Data sheet ( Hoja de datos )
| Número de pieza | MX25L25835E | |
| Descripción | FLASH MEMORY | |
| Fabricantes | MACRONIX | |
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MX25L25835E
MX25L25835E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1737
REV. 1.0, NOV. 29, 2011
1
http://www.Datasheet4U.com
1 page  
MX25L25835E
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features Independently at each 128Mb Flash memory
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state first.)
• Status Register Feature Independently at each 128Mb Flash memory
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- REMS, REMS2 and REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID
HARDWARE FEATURES
• CS#1 & CS#2
- Both CS#1 and CS#2 are Chip Select inputs. CS#1 and CS#2 can select different 128Mb Flash memories
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O mode
• HOLD#/SIO3
- To pause the device without deselecting the device or serial data Input or serial data Input/Output for 4 x I/O
mode
• RESET#
- Hardware Reset Pin
• PACKAGE
- 16-pin SOP (300mil)
- All devices are RoHS Compliant
P/N: PM1737
REV. 1.0, NOV. 29, 2011
5
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5 Page 
MX25L25835E
888DATA PROTECTION
MX25L25835E is stacked by two 128Mb Flash memories. These two memories are independent. All the commands
will only affect the selected 128Mb Flash memory. MX25L25835E is designed to offer protection against accidental
erasure or programming caused by spurious system level signals that may exist during power transition. During
power up the device automatically resets the state machine in the standby mode. In addition, with its control reg-
ister architecture, alteration of the memory contents only occurs after successful completion of specific command
sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC
power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before is-
suing other commands to change data. The WEL bit will return to reset stage under following situations:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection at each 128Mb Flash memory
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
If the system goes into four I/O mode, the feature of HPM will be disabled.
- MX25L25835E provides individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for in-
dividual block (or sector) unprotect. Under the mode, user may conduct whole chip protect with GBLK instruction
and unlock the whole chip with GBULK instruction.
Note: The term "chip" only refers to the selected 128Mb Flash memory.
P/N: PM1737
11
REV. 1.0, NOV. 29, 2011
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX25L25835E.PDF ] | |
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