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PDF TMP86FH09NG Data sheet ( Hoja de datos )
| Número de pieza | TMP86FH09NG | |
| Descripción | 8 Bit Microcontroller | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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8 Bit Microcontroller
TLCS-870/C Series
TMP86FH09NG
November 10, 2005
Free Datasheet http://www.Datasheet4U.com
1 page  
tentative
TMP86FH09NG
1.2 Pin Assignment
P-SDIP32-400-1.78
VSS
XIN
XOUT
TEST
(VAREF/AVDD) VDD
(XTIN) P21
(XTOUT) P22
RESET
(STOP/INT5) P20
(TXD) P00
(RXD) P01
(SCLK) P02
(MOSI) P03
(MISO) P04
P14
P16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 P37 (AIN5/STOP5)
31 P36 (AIN4/STOP4)
30 P35 (AIN3/STOP3)
29 P34 (AIN2/STOP2)
28 P33 (AIN1)
27 P32 (AIN0)
26 P31 (TC4/PDO4/PWM4/PPG4)
25 P30 (TC3/PDO3/PWM3)
24 P12 (DVO)
23 P11 (INT1)
22 P10 (INT0)
21 P07 (TC1/INT4)
20 P06 (INT3/PPG)
19 P05 (SS)
18 P13
17 P15
Figure 1-1 Pin Assignment
Page 5
Free Datasheet http://www.Datasheet4U.com
5 Page 
tentative
TMP86FH09NG
Timing Generator Control Register
TBTCR
(0036H)
7
(DVOEN)
65
(DVOCK)
4
DV7CK
3
(TBTEN)
210
(TBTCK)
(Initial value: 0000 0000)
DV7CK
Selection of input to the 7th stage
of the divider
0: fc/28 [Hz]
1: fs
R/W
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
2.2.2.2 Machine cycle
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc or 1/fs [s]
Main system clock
State
S0 S1 S2 S3 S0 S1 S2 S3
Machine cycle
Figure 2-5 Machine Cycle
2.2.3 Operation Mode Control Circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-
frequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.
2.2.3.1 Single-clock mode
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
(1) NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
The TMP86FH09NG is placed in this mode after reset.
Page 11
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11 Page | ||
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