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PDF STM8AF519A Data sheet ( Hoja de datos )
| Número de pieza | STM8AF519A | |
| Descripción | Automotive 8-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STM8AF61xx, STM8H61xx
STM8AF51xx, STM8AH51xx
Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM,
10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 V to 5.5 V
Features
Core
■ Max fCPU: 24 MHz
■ Advanced STM8A core with Harvard
architecture and 3-stage pipeline
■ Average 1.6 cycles/instruction resulting in 10
MIPS at 16 MHz fCPU for industry standard
benchmark
Memories
■ Program memory: 48 to 128 Kbytes Flash; data
retention 20 years at 55 °C after 1 kcycle
■ Data memory: 1.5 to 2 Kbytes true data
EEPROM; endurance 300 kcycles
■ RAM: 3 to 6 Kbytes
Clock management
■ Low power crystal resonator oscillator with
external clock input
■ Internal, user-trimmable 16 MHz RC and low
power 128 kHz RC oscillators
■ Clock security system with clock monitor
Reset and supply management
■ Multiple low power modes (wait, slow, auto
wake-up, halt) with user definable clock gating
■ Low consumption power-on and power-down
reset
Interrupt management
■ Nested interrupt controller with 32 interrupt
vectors
■ Up to 37 external interrupts on 5 vectors
Timers
■ Up to 2 auto-reload 16-bit PWM timers with up
to 3 CAPCOM channels each (IC, OC or PWM)
■ Multipurpose timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
■ 8-bit AR system timer with 8-bit prescaler
■ Auto wake-up timer
■ 2 watchdog timers: Window and standard
LQFP48 7x7
LQFP80 14x14
LQFP64 10x10
LQFP32 7x7
Communication interfaces
■ High speed 1 Mbit/s active CAN 2.0B interface
■ USART with clock output for synchronous
operation - LIN master mode
■ LINUART LIN 2.1 compliant, master/slave
modes with automatic resynchronization
■ SPI interface up to 10 Mbit/s or (fCPU/2)
■ I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
■ 10-bit, 3 LSB ADC with up to 16 multiplexed
channels
I/Os
■ Up to 70 user pins including 10 high sink I/Os
■ Highly robust I/O design, immune against
current injection
Table 1. Device summary(1)
STM8AF61xx/STM8AH61xx (without CAN)
STM8AF/H61AA, STM8AF/H619A, STM8AF/H61A9,
STM8AF/H6199, STM8AF/H6189, STM8AF/H6179,
STM8AF/H6169, STM8AF/H61A8, STM8AF/H6198,
STM8AF/H6188, STM8AF/H6178, STM8AF/H6186,
STM8AF/H6176
STM8AF51xx/STM8AH51xx (with CAN)
STM8AF/H51AA, STM8AF/H519A, STM8AF/H51A9,
STM8AF/H5199, STM8AF/H5189, STM8AF/H5179,
STM8AF/H5169, STM8AF/H51A8, STM8AF/H5198,
STM8AF/H5188, STM8AF/H5178
1. This datasheet applies to product versions with and
without data EEPROM. The order code identifier is ‘F’
or ‘H’ respectively, only one of which appears in an
order code.
August 2008
Rev 2
1/100
www.st.com
1
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1 page  
STM8AF61xx, STM8AF51xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8AF/H51xx product line-up - with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STM8AF/H61xx product line-up - without CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STM8A timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviation for Table 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stack and RAM partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM8A I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM8A general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Total current consumption in run, wait and slow mode at VDD = 5.0 V. . . . . . . . . . . . . . . . 59
Total current consumption and timing in halt, fast active halt and slow
active halt modes at VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Total current consumption in run, wait and slow mode at VDD = 3.3 V. . . . . . . . . . . . . . . . 61
Total current consumption and timing in halt, fast active halt and slow
active halt modes at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical peripheral current consumption VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TIM 1, 2, 3 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5/100
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STM8AF61xx, STM8AF51xx
4 Block diagram
Figure 1. STM8A block diagram
Block diagram
Reset
Single wire
debug interf.
Master/slave
autosynchro
400 Kbit/s
10 Mbit/s
LIN master
SPI emul.
1 Mbit/s
16 channels
Reset block
Reset
POR
PDR
Clock controller
Detector
XTAL 1-24 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock to peripherals and core
STM8A CORE
Debug/SWIM
LINUART
I2C
SPI
USART
beCAN
10-bit ADC
Window WDG
WDG
Up to 128 Kbyte
program
Flash
Up to 2 Kbytes
data EEPROM
Up to 6 Kbytes
RAM
Boot ROM
16-bit multi-purpose
timer (TIM1)
16-bit PWM timers
(TIM2, TIM3)
8-bit AR timer
(TIM4)
AWU timer
Up to
9 CAPCOM
channels
11/100
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11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet STM8AF519A.PDF ] | |
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