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PDF TY72011AP2 Data sheet ( Hoja de datos )
| Número de pieza | TY72011AP2 | |
| Descripción | Single Ended PWM Controller Featuring QR Operation and Soft Frequency Foldback | |
| Fabricantes | ON Semiconductor | |
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Customer Specific Device from ON Semiconductor
TY72011AP2
Advance Information
Single Ended PWM
Controller Featuring QR
Operation and Soft
Frequency Foldback
The TY72011AP2 combines a true Current Mode Control
modulator and a demagnetization detector to ensure full
Discontinuous Conduction Mode in any load/line
conditions and minimum drain voltage switching
(Quasi-Resonant operation). Thanks to its inherent Variable
Frequency Mode (VFM), the controller decreases its
operating frequency at constant peak current whenever the
output power demand diminishes. Associated with
automatic multiple valley switching, this unique
architecture guarantees minimum switching losses and the
lowest power drawn from the mains when operating at
no-load conditions. The internal High-Voltage current
source provides a reliable charging path for the Vcc
capacitor and ensures a clean and short start-up sequence
without deteriorating the efficiency once off.
Finally, the continuous feedback signal monitoring
implemented with an over-current fault protection circuitry
(OCP) makes the final design rugged and reliable. An
internal Over Voltage Protection (OVP) circuit continuously
monitors the Vcc pin and stops the IC whenever its level
exceeds 40 V. The internal OVP connection is also
externally available to precisely adjust the final protection
level to the designer needs.
ORDERING INFORMATION
Device
Package
Shipping
Features
• Natural Drain-Source Valley Switching for Lower EMI
and Quasi-Resonant Operation
• Current Mode Control
• Smooth Frequency Foldback for Low Standby Power
and Minimum Output Ripple at No-Load
• Internal 200 ns Leading Edge Blanking on Current
Sense
• Wide UVLO Levels: 9.3 to 15 V Typical
• 250 mA Sink and Source Driver
• Wide Operating Voltages: 8.0 to 36 V with Fixed Over
Voltage Protection (OVP) on the VCC or Adjustable
through a Dedicated Pin
• Internal Short-Circuit Protection
• Integrated 3.0 mA Typ. Start-Up Source
Applications
• Off-Line Charger
• Standby SMPS
• Wall Adapters
• Power Supplies For:
DVD Players
Set-Top Boxes, etc.
TYP2011AP2
TYP2011AP2G
PDIP-14
PDIP-14
(Pb-Free)
14
1
PDIP-14
P SUFFIX
CASE 646
25 Units/Rail
25 Units/Rail
MARKING
DIAGRAM
1
TY72011AP2
AWLYYWWG
14
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
PIN CONNECTIONS
HV 1
NC 2
Demag 3
FB 4
Ct 5
OVP 6
NC 7
14 NC
13 VCC
12 Drive
11 Isense
10 GND
9 NC
8 NC
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
©Ă Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 2
1
Publication Order Number:
TY72011AP2/D
Free Datasheet http://www.datasheet-pdf.com/
1 page  
TY72011AP2
ELECTRICAL CHARACTERISTICS (continued) (For typical values TA = 25°C, for min/max values TA = -25°C to +85°C,
Max TJ = 150°C, VCC = 12 V unless otherwise noted.)
Characteristics
Pin #
Symbol
Min
Typ
Max
Unit
Current Comparator (continued)
Propagation Delay from Current Detection to Gate OFF
State
11 Tdel
-
200 250 ns
Leading Edge Blanking (LEB)
11 Tleb
-
200
- ns
Variable Frequency Modulator
Minimum Frequency Operation @ Ct = 1.0 hF and
VCC = 35 V
Maximum Frequency Operation @ Ct = 1.0 hF and
VCC = 35 V
Minimum Ct Charging Current (Note 1)
Maximum Ct Charging Current (Note 1)
Discharge Time @ Ct = 1.0 hF
5 Fmin - 0 - kHz
5
Fmax
90
110 125 kHz
5 ICtmin - 0 - mA
5
ICtmax
280
350
420 mA
5 - - 500 - ns
Drive Output
Output Voltage Rise Time @ CL = 1.0 hF (DV = 10 V)
Output Voltage Fall Time @ CL = 1.0 hF (DV = 10 V)
Clamped Output Voltage @ VCC = 35 V (Note 2)
Voltage Drop on the Stage @ VCC = 10 V (Note 2)
Undervoltage Lockout
Startup Threshold (VCC Increasing)
Minimum Operating Voltage (VCC Decreasing)
Internal Startup Current Source
Maximum Voltage, Pin 1 Grounded
Maximum Voltage, Pin 1 Decoupled (470 mF)
Startup Current Flowing through Pin 1
Leakage Current in Offstate @ Vpin 1 = 500 V
12 tr
-
12 tf
-
12 VDRV 11
12 VDRV
-
60 100 ns
40 100 ns
13 16 V
- 0.5 V
13
UVLOH
13.5
15
16.5 V
13
UVLOL
8.3
9.3 10.0 V
1 - - 450 - V
1 - - 500 - V
1 - 2.5 3.0 4.5 mA
1 - - 32 70 mA
Device Current Consumption
VCC less than UVLOH
VCC = 35 V and Fsw = 2.0 kHz, CL = 1.0 hF
VCC = 35 V and Fsw = 125 kHz, CL = 1.0 hF
Startup Current to VCC Capacitor
1. Typical capacitor swing is between 0.5 V and 3.5 V.
2. Guaranteed by design, TJ = 25°C.
13 - - 1.5 1.8 mA
13 - - 1.2 3.0 mA
13 - - 3.0 4.0 mA
13 - 1.5
-
- mA
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5
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5 Page 
TY72011AP2
6.500
4.500
2.500
1.5 V
Regulation Area
FB
Virtual Point
500.0 M
OCP Condition
Error Flag
1.000 M 3.000 M 5.000 M 7.000 M 9.000 M
Figure 8.
As soon as the system recovers from the error, e.g. FB is
back within its regulation area, the IC operation comes back
to normal.
To avoid any system thermal runaway, another internal
8 x 128 ms delay is combined with the previous 128 ms. It
works as follow: the 128 ms delay is provided to account for
any normal transients that engender a temporary loss of
feedback (FB goes toward ground). However, when the
128 ms period is actually over (the feedback is definitively
lost) the IC stops the output driving pulses for a typical
period of 8 x 128 ms. During this mode, the rest of the
functions are still activated. For instance, in lack of pulses,
the self-supplied being no longer provided, the start-up
source turns on and off (when reaching the corresponding
UVLOL and UVLOH levels), creating an hiccup waveform
on the Vcc line. As soon as the feedback condition is
restored, the 8 x 128 ms is interrupted and, in synchronism
with the Vcc line, the IC is back to normal. The following
diagrams show how this mechanism takes place when FB is
down to zero (optocoupler opened) or up to Vcc
(optocoupler shorted). If we assume that the error is
permanently present, then a burst mode takes place with a
128/8 x 128 = 12.5% duty-cycle. The real transmitted
power is thus:
PoutBURST + 12Ă ·ĂLpĂ·ĂIp2Ă·ĂFswĂ·ĂDutyBURST
Over Voltage Conditions (OVP) are detected by
monitoring the Vcc level. As Figure 9 describes, three 10 V
zener plus one 5.0 V zener are connected in series together
with a 18 kW to ground. As soon as Vcc exceeds 40 V
typical, a current starts to flow in the 18 k resistor. When the
voltage developed across this element exceeds 2.5 V, an
error is triggered and immediately latches the IC off. In lack
of switching pulses, the Vcc capacitor is no longer refreshed
by the auxiliary supply and slowly discharges toward
ground. When the Vcc level crosses UVLOL, a new startup
sequence occurs. If the OVP has gone, normal IC operation
takes place. For different OVP levels, the comparator input
is accessible through pin 6.
Latched
OVP
2
7
1
+
2.5 V
VCC
6
5V
5
10 V
4
10 V
3
10 V
2k 8
18 k
OVP
Figure 9.
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11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet TY72011AP2.PDF ] | |
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