GS8342T08E-167 Datasheet PDF - GSI Technology
Part Number | GS8342T08E-167 | |
Description | (GS8342Txxx) 36Mb SigmaCIO DDR-II Burst of 2 SRAM | |
Manufacturers | GSI Technology | |
Logo | ||
There is a preview and GS8342T08E-167 download ( pdf file ) link at the bottom of this page. Total 30 Pages |
Preview 1 page No Preview Available ! Preliminary
GS8342T08/09/18/36E-333/300/267*/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaCIO DDR-II
Burst of 2 SRAM
167 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb
and 144Mb devices
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
SigmaCIO™ Family Overview
The GS8342T08/09/18/36E are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342T08/09/18/36E SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342T08/09/18/36E SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
http://www.DataSheet4U.net/
Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs
always transfer data in two packets. When a new address is
loaded, A0 presets an internal 1 bit address counter. The
counter increments by 1 (toggles) for each beat of a burst of
two data transfer.
Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer
data in two packets. When a new address is loaded, the LSB
is internally set to 0 for the first read or write transfer, and
incremented by 1 for the next transfer. Because the LSB is
tied off internally, the address field of a x8 SigmaCIO DDR-II
B4 RAM is always one address pin less than the advertised
index depth (e.g., the 8M x 8 has a 2M addressable index).
tKHKH
tKHQV
Parameter Synopsis
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-267*
3.75 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
* The 267 MHz speed bin is only available on the x18 part.
Rev: 1.02 8/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
datasheet pdf - http://www.DataSheet4U.net/
|
|
Preliminary
GS8342T08/09/18/36E-333/300/267*/250/200/167
4M x 8 SigmaCIO DDR-II SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A
CQ
MCL/SA
(72Mb)
SA
R/W NW1
K
NC LD SA SA CQ
B NC NC NC SA NC K NW0 SA NC NC DQ3
C NC NC NC VSS SA SA SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ0
http://www.DataSheet4U.net/
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ7 SA SA C SA SA NC NC NC
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 is set to 0 at the
beginning of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7
3. MCL = Must Connect Low
Rev: 1.02 8/2005
5/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
datasheet pdf - http://www.DataSheet4U.net/
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for GS8342T08E-167 electronic component. |
Information | Total 30 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ GS8342T08E-167.PDF Datasheet ] |
Share Link :
Electronic Components Distributor
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
Part Number | Description | MFRS |
GS8342T08E-167 | The function is (GS8342Txxx) 36Mb SigmaCIO DDR-II Burst of 2 SRAM. GSI Technology | |
GS8342T08E-167I | The function is (GS8342Txxx) 36Mb SigmaCIO DDR-II Burst of 2 SRAM. GSI Technology | |
Semiconductors commonly used in industry:
1N4148 |  
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
GS83
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA |