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PDF UBA20271 Data sheet ( Hoja de datos )

Número de pieza UBA20271
Descripción (UBA20271 / UBA20272) 350 V and 600 V Power ICs
Fabricantes NXP Semiconductors 
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UBA20271/2
350 V and 600 V Power ICs for dimmable compact fluorescent
lamps
Rev. 2.1 — 12 October 2011
Product data sheet
1. General description
The UBA20271/2 are high-voltage power ICs intended to drive and control higher
powered self ballasted Compact Fluorescent Lamp (CFL) lighting applications. The
UBA20271/2 operate from 120 V and 230 V. The module includes a half-bridge power
circuit of two NMOST power FETs. In addition, a controller circuit is included that has
advanced features for dimming and a lamp current controlled boost feature. The boost
feature is used for boosting cold (amalgam) CFL.
The controller contains a half-bridge drive function for CFL, a high-voltage level-shift
circuit with integrated bootstrap diode. In addition, the controller contains an oscillator
function, a current control function both for preheat and burn, a timer function and
protection circuits. The UBA20271/2 are supplied via a dV/dt current charge supply circuit
from the half-bridge circuit.
Remark: Mains voltages noted are AC.
2. Features and benefits
2.1 Half-bridge features
UBA20271: Two internal 350 V, 1.0  max 5.0 A NMOST half-bridge power FETs
UBA20272: Two internal 600 V, 3.0 , max 2.7 A NMOST half-bridge power FETs
Integrated high-voltage level-shift function with integrated bootstrap diode
2.2 Preheat and ignition features
Coil saturation protection during ignition
Adjustable saturation protection level
Adjustable preheat time
Adjustable preheat current
Ignition lamp current detection
2.3 Lamp boost features
Adjustable boost timing
Fixed boost current ratio of 1.5
Gradually boost to burn transition timing
2.4 Dim features
Continuously variable dimming function for standard phase cut dimmers
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NXP Semiconductors
UBA20271/2
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
7. Functional description
The UBA20271/2 are ICs with integrated half-bridge MOSFETs in self ballasted
high-power CFL and their derivatives. The UBA20271/2 are equipped with variable
dimming functionality that has a logarithmic corrected natural dimming function. This
function enables a less sensitive brightness control of the lamp at low dim levels.
The UBA20271/2 are rated up to a maximum continuous rectified mains voltage of 350 V
or 500 V, respectively and lamp power-up to 20 W. The UBA20271/2 include all the
necessary functions for preheat, ignition, boost, and on-state operation of the lamp and
includes a linear dimming feature. In addition, several protection measures are included
that safeguard the functioning of the CFL and controller. The controller states are shown
in Figure 3.
VDD = 0
RESET STATE
HOLD = 0
VDD < VDD(rst)
VDD > VDD(rst)
VDD < VDD(rst)
START-UP STATE
VCP < Vth(rel)CP
POWER-DOWN STATE
(1)
PREHEAT STATE
UBA20271_UBA20272
Product data sheet
preheat time
completed
IGNITION STATE
(2)
HOLD STATE
(3)
HOLD = 1
(4)
Ignition_Detected
(6) BOOST AND BURN
STATES
(5)
001aam665
(1) VDD > VDD(start) AND Vi(DCI) > Vth(start)DCI AND (HOLD = 0 OR VCP < Vth(rel)CP)
(2) VDD < VDD(stop) OR Vi(DCI) < Vth(start)DCI Vth(hys)DCI
(3) (End of ignition time AND HOLD = 0) OR VDD < VDD(stop) OR Vi(DCI) < Vth(start)DCI Vth(hys)DCI
(4) End of ignition AND HOLD = 1
(5) VCP < Vth(pd)CP OR overcurrent fault time > 110 tph OR fbridge(max) detected in capacitive mode
(6) VDD < VDD(stop) OR Vi(DCI) < Vth(start)DCI Vth(hys)DCI
Fig 3. State diagram
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 12 October 2011
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
UBA20271/2
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
When CP is lower than Vth(rel)CP, the IC is released from the hold state and moves to the
start-up state. See Figure 3. Alternatively, the hold state ends when the supply voltage is
lower than VDD(rst) and the IC is reset.
With a 470 nF capacitor on the CP pin, the typical hold state retention delay is between
1.0 seconds and 1.7 seconds. However, it depends on where the preheat cycle is cut off
on the rising or falling edge of the preheat timing. The retention time for a failed ignition
always starts from the top of the rising edge on the CP pin. See Figure 5. In the hold state,
a latch is set (hold state latch = 1), the oscillator is stopped, transistor HS is
non-conductive and transistor LS conducting. The voltage on pin VDD alternates between
VDD(start) and VDD(stop) as long as the voltage on the CP pin has not reached Vth(rel)CP. See
Figure 5.
The alternating supply voltage is a result of the current drawn by the IC supply pin VDD.
The supply current is less than 220 A, when the supply voltage VDD is increasing
between VDD(stop) and VDD(start). The supply current is typically 2 mA when VDD is
decreasing between VDD(start) and VDD(stop). More current is drawn during the decreasing
slope of VDD as the internal analog supply is turned on when VDD > VDD(start). This
condition enables comparators in the IC to monitor the voltage on the CP pin and whether
the supply voltage VDD decreases lower than VDD(stop).
7.2 Oscillation and timing
7.2.1 Oscillation
The internal oscillator is a VCO circuit which generates a sawtooth waveform between the
Vth(CF)max level and 0 V. Capacitor CCF, resistor Rext(RREF), and the voltage at the CI pin
determine the frequency of the sawtooth. Rext(RREF) and CCF determine the minimum and
maximum switching frequencies. Their ratio is internally fixed. There are two ratios, the
ratio between fbridge(max) and fbridge(min) is 2.5 and the ratio between fbridge(max) and
fbridge(bst)min is 4.6. The sawtooth frequency is twice the half-bridge frequency.
Transistors HS (Q1) and LS (Q2) are brought into conduction with a duty cycle of
approximately 50 %. Figure 8 provides an overview of the oscillator signal and driver
signals. The oscillator starts oscillating at fbridge(max). The non-overlap time between the
gate drive signals VGLS and VGHS is tno.
UBA20271_UBA20272
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 12 October 2011
© NXP B.V. 2011. All rights reserved.
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