PDF L74VHC1GT00 Data sheet ( Hoja de datos )

Número de pieza	L74VHC1GT00
Descripción	2-Input NAND Gate / CMOS Logic Level Shifter
Fabricantes	LRC
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Hay una vista previa y un enlace de descarga de L74VHC1GT00 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas
No Preview Available ! LESHAN RADIO COMPANY, LTD. 2–Input NAND Gate / CMOS Logic Level Shifter with LSTTL–Compatible Inputs L74VHC1GT00 The L74VHC1GT00 is a single gate 2–input NAND fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power supply. The L74VHC1GT00 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the L74VHC1GT00 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc. • High Speed: t PD = 3.1 ns (Typ) at V CC = 5 V • Low Power Dissipation: I CC = 2mA (Max) at T A = 25°C • TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V • CMOS–Compatible Outputs: V OH > 0.8 V CC ; V OL < 0.1 V CC @Load • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Chip Complexity: FETs = 64; Equivalent Gates = 14 5 4 1 2 3 SC–70/SC–88A/SOT–353 DF SUFFIX 5 4 1 2 3 SOT–23/TSOP–5/SC–59 DT SUFFIX PIN ASSIGNMENT 1 IN B 2 IN A 3 GND 4 OUT Y 5 V CC www.DataSheet4U.com MARKING DIAGRAMS VHd Pin 1 d = Date Code Y Figure 1. Pinout (Top View) VHd Figure 2. Logic Symbol Pin 1 d = Date Code FUNCTION TABLE Inputs A L L H H B L H L H Output Y H H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 1/6 1 page LESHAN RADIO COMPANY, LTD. A G 54 S −B− 12 3 L74VHC1GT00 PACKAGE DIMENSIONS SC70−5/SC−88A/SOT−353 DF SUFFIX D 5 PL 0.2 (0.008) M B M N C J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. INCHES DIM MIN MAX A 0.071 0.087 B 0.045 0.053 C 0.031 0.043 D 0.004 0.012 G 0.026 BSC H −−− 0.004 J 0.004 0.010 K 0.004 0.012 N 0.008 REF S 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC −−− 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 HK SOLDERING FOOTPRINT* 0.50 0.0197 0.40 0.0157 0.65 0.025 0.65 0.025 1.9 0.0748 ǒ ǓSCALE 20:1 mm inches 5/6 5 Page

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