74HCT4053 Datasheet PDF - NXP Semiconductors
Part Number | 74HCT4053 | |
Description | Triple 2-Channel Analog Multiplexer / Demultiplexer | |
Manufacturers | NXP Semiconductors | |
Logo | ||
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Triple 2-channel analog multiplexer/demultiplexer
Rev. 9 — 10 February 2016
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a triple single-pole double-throw analog switch (3x SPDT)
suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch
features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a
common input/output (nZ). A digital enable input (E) is common to all switches. When E is
HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Wide analog input voltage range from 5 V to +5 V
Complies with JEDEC standard no. 7A
Low ON resistance:
80 (typical) at VCC VEE = 4.5 V
70 (typical) at VCC VEE = 6.0 V
60 (typical) at VCC VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical ‘break before make’ built-in
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
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NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
7. Functional description
Table 3.
Inputs
E
L
L
H
Function table [1]
Sn
L
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Channel on
nY0 to nZ
nY1 to nZ
switches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
ISK
ISW
IEE
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VSW < 0.5 V or VSW > VCC + 0.5 V
0.5 V < VSW < VCC + 0.5 V
SO16, (T)SSOP16, and
DHVQFN16 package
[1]
[2]
0.5
-
-
-
-
-
-
65
-
+11.0
20
20
25
20
50
50
+150
500
V
mA
mA
mA
mA
mA
mA
C
mW
P
power dissipation
per switch
- 100 mW
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC supply voltage
VI input voltage
VSW switch voltage
see Figure 7
and Figure 8
VCC GND
VCC VEE
74HC4053
Min Typ Max
2.0
2.0
GND
VEE
5.0
5.0
-
-
10.0
10.0
VCC
VCC
74HCT4053
Unit
Min Typ Max
4.5
2.0
GND
VEE
5.0
5.0
-
-
5.5
10.0
VCC
VCC
V
V
V
V
74HC_HCT4053
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 10 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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