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PDF CYONS2001 Data sheet ( Hoja de datos )
| Número de pieza | CYONS2001 | |
| Descripción | Wireless Laser Navigation System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
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CYONS2001
OOvavatiotionnOONNSS™™IIII
WWireirleelsessLaLsaesrerNNavaivgiagtaiotinonSSysytsetmem-o-no-nC-Chihpip
Features
■ Programmable blocks
❐ HpriogghrlyaminmteagbraletePdSwoiCre®lemssicmroocuosnetr-oolnle-ra-ucnhitip(MwCithU)
❐ 16 KB flash memory
❐ 2 KB static RAM (SRAM)
❐ Internal 24-, 12-, or 6-MHz main oscillator (IMO)
❐ Internal 32-kHz low speed oscillator (ILO)
❐ 16-bit data report enables simultaneous high speed and high
resolution tracking
■ Tracking performance
❐ Selectable resolution of 400, 800, or 1600 counts per inch
(CPI), independent of speed
❐ High speed with high accuracy tracking
❐ Speed up to 30 inches per second (in/s)
❐ Acceleration up to 20 g
■ Peripheral Interface
❐ SPI master interface to radio for wireless applications
❐ Fast or standard mode I2C
■ 28 general purpose input/output (GPIO) pins
❐ Port 0 – 8 bits
❐ Port 1 – 8 bits with high current capability, regulated output
voltage, and 5 V input tolerance
❐ Port 2 – 8 bits
❐ Port 3 – 4 bits
■ Power
❐ Internal power system enables operation from battery or
external 2.7 to 3.6 V supply
❐ Battery input voltage of 0.8 V to 3.6 V enables operation from
single or dual series cells
❐ Self adjusting power saving modes
■ On-chip laser
❐ Vertical cavity surface emitting laser (VCSEL) integrated
within the sensor package
❐ No calibration or alignment needed
❐ Electrostatic discharge (ESD) immunity: 2000 V human body
model (HBM)
❐ Wavelength: 840 to 870 nm
❐ IEC 60825-1 Class 1 safety: built-in eye-safe fault tolerant
laser drive circuitry
■ Snap-on lens
❐ Molded optic: Self-aligning snap-on molded lens
❐ 6 mm distance between the printed circuit board (PCB) and
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Description
The CYONS2001 is a member of Cypress Semiconductor’s
second generation laser navigation system-on-chip (SoC) family
of products. Powered by the high speed and high precision
OptiCheck™ technology, along with the world leading PSoC
technology, this family integrates the sensor, boost power
regulator, and MCU functions into one chip. Bundled with the
VCSEL into one package, the combination forms the market’s
first true mouse-on-a-chip solution.
The CYONS2001 is the version that is designed for general
purpose wireless mouse applications. Enabled by the Cypress
0.13-micron mixed signal process technology, the device
integrates the OptiCheck sensor with MCU into a single silicon
chip that enables seamless communication between sensor and
a wireless radio integrated circuit (IC). The sensor provides the
best translation of precise hand motion into cursor motion on the
PC.
This highly integrated solution is programmable. It provides
mouse suppliers the ease-of-use to design a single PCB system
and customize their product. With the VCSEL integrated in the
same package, designers do not need to calibrate the laser
power during the manufacturing process. This greatly increases
production throughput and reduces manufacturing costs.
The innovative technology of OvationONS™ II provides high
precision, high speed motion tracking, and low power
consumption. Designers can select from a family of integration
options, ranging from low power to high performance, to target
different types of wired and wireless design applications.
The CYONS2001 solutions have a small form factor. Along with
the lens, each package forms a complete and compact laser
tracking system. This datasheet describes the detailed
technology capabilities of the CYONS2001.
Figure 1. CYONS2001/CYONSLENS2000 (2-Piece System)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44045 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 3, 2011
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CYONS2001
Pin Description
This section describes, lists, and illustrates the CYONS2001 device pins and pinout configurations. The CYONS2001 is available in
a 42-pin quad flat no-leads (QFN) package.
Table 1. CYONS2001 Pin Description
Pin
1
2
3
4
5
Name
XRES
BOOST_GND
BOOST_IND
VBATT
DVDD
6 VREGD
7 AVDD
8 VREGA
9 P2[7]
10 P1[5]
11 P1[3]
12 P2[3]
13 P2[5]
14 P1[7]
15 P1[1]
16 P3[3]
17 P1[0]
18 P3[5]
19 P1[6]
20 P1[2]
21 P2[2]
22 P3[7]
23 P3[1]
24 OCDE
25 AVSS
26 P2[1]
27 P2[0]
28 P1[4]
29 P2[4]
30 DVSS
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32 P0[0]
33 P0[2]
34 P0[4]
35 P0[6]
36 P0[1]
Digital
I
Power
Power
Power
Power
Power
Power
Power
I/O
IOHR
IOHR
I/O
I/O
IOHR
IOHR
IOHR
I/O
I/O
IOHR
IOHR
I/O
I/O
I/O
OCD
Power
I/O
I/O
IOHR
I/O
Power
I/O
I/O
I/O
I/O
I/O
I/O
Analog
Power
Power
Power
Power
Power
Power
Power
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
OCD
Power
I
I
I
I
Power
I
I
I
I
I
I
Notes
Active high external reset with internal pull down
Boost regulator ground
Boost regulator inductor
Boost regulator input
Digital supply voltage and regulated output (see Power Supply
Connections on page 11)
Digital VREG
Analog supply voltage
Analog VREG
GPIO port 2 pin 7
SPI MISO, I2C_SDA, GPIO port 1 pin 5
SPI CLK, GPIO port 1 pin 3
GPIO port 2 pin 3
GPIO port 2 pin 5
SPI SS, I2C_SCL, GPIO port 1 pin 7
SPI MOSI, ISSP CLK[1], I2C_SCL, GPIO port 1 pin 1
HCLK (OCD high speed clock output), GPIO port 3 pin 3
ISSP DATA[1], I2C_SDA, GPIO port 1 pin 0
CCLK (OCD CPU clock output), GPIO port 3 pin 5
GPIO port 1 pin 6
GPIO port 1 pin 2
GPIO port 2 pin 2
OCDOE (OCD mode direction pin), GPIO port 3 pin 7
OCDO (OCD odd data output), GPIO port 3 pin 1
OCDE (OCD even data output)
Analog ground
GPIO port 2 pin 1
GPIO port 2 pin 0
EXT CLK, GPIO port 1 pin 4
GPIO port 2 pin 4
Digital ground
GPIO port 2 pin 6
GPIO port 0 pin 0
GPIO port 0 pin 2
GPIO port 0 pin 4
GPIO port 0 pin 6
GPIO port 0 pin 1
Document Number: 001-44045 Rev. *G
Page 5 of 35
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5 Page 
Power Supply Connections
Figure 4. Power Connections
Battery
0.8 - 3.6V
VBATT 4
47 uH
External 3.3V
Supply, 15
mA max
22
uF
Digital
GND
BOOST_IND 3
DVDD 5
10 nH
AVDD 7
22 22
uF uF
VREGD 6
Digital
GND
Analog
GND
VREGA 8
1.8V Analog
Regulator
CYONS2001
Boost
Regulator
Battery
Filter
1.8V PSoC
Core
Regulator
Global
Analog
Interconnect
1.8V Analog
Circuitry
3V Analog
Circuitry
1.8V Digital
Circuitry
3V Digital
Circuitry
CYONS2001
Digital
GND
Analog
GND
Analog
GND
Digital
GND
Digital
GND
Overview
The CYONS2001 incorporates a powerful and flexible powering
system. It can be powered from one of two sources: a battery
(one cell or two cells in series) or an external 3.3-V supply.
Additionally, the CYONS2001’s internal regulators can supply
current to external devices. This section describes the
capabilities and usage of the power system. Refer to Figure 4 for
a block diagram of the CYONS2001’s power system.
Understanding DVDD
DVDD is a unique pin that can serve as either an input or an
output. When the device is powered from a battery (using the
boost regulator), DVDD acts as an output, providing a 3.3-V
voltage that can be used to power AVDD, VREGD, VREGA, and
external parts. When the device is powered from an external
3.3-V supply, DVDD acts as an input only.
AVDD, VREGA, and VREGD
As with DVDD, these signals power the internal circuitry of the
device. Unlike DVDD, these are always inputs. They should be
connected as shown in Figure 4.
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For wireless applications, the device may be powered by the
boost regulator. In this configuration, BOOST_GND should be
connected to DVSS, BOOST_IND, and VBATT pins should be
connected as shown in Figure 4. Do not run the device without
the appropriate bypass capacitors, or excessive voltage may be
generated across the inductor.
VBATT connects to an internal low pass filter. The filter output
can be routed through the global analog interconnect to the
device’s ADC, enabling the battery voltage to be monitored.
For designs using two series batteries, an option is to drive
VREGA directly from the battery output. Doing so reduces the
conversion loss in the boost regulator. However, care must be
taken to ensure that the battery voltage does not fall below
1.71 V.
Using External Power
The CYONS2001 can also be powered from an external source.
In this case, BOOST_GND should be connected to DVSS,
VDD5V, and BOOST_IND should be left unconnected, and the
external 3.3-V source should connect to DVDD. VBATT can be
connected to DVSS or left unconnected.
Filtering and Grounding
For all designs, it is important to provide proper grounding and
proper isolation between the analog and digital power supplies.
The analog and digital grounds should be isolated, except for a
single connection point that is placed very close to the device.
On the supply side, a L-C filter should be placed between AVDD
and DVDD, as shown in Figure 4.
Document Number: 001-44045 Rev. *G
Page 11 of 35
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| PDF Descargar | [ Datasheet CYONS2001.PDF ] | |
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