PDF STC4130 Data sheet ( Hoja de datos )

Número de pieza	STC4130
Descripción	Synchronous Clock
Fabricantes	Connor-Winfield
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No Preview Available ! STC4130 Synchronous Clock for SETS Data Sheet Description The STC4130 is a ROHS compatible, integrated, single chip solution for the synchronous clock in SDH and SONET network elements. The device is fully compliant with ITU-T G.812 Type III, G.813, and Telcordia GR1244, and GR253. The STC4130 accepts 12 reference inputs and gen- erates 8 independent synchronized output clocks. Reference input frequencies are automatically detected, and inputs are individually monitored for quality. Active reference selection may be manual or automatic. All reference switches are hitless. Syn- chronized outputs may be programmed for a wide variety of SONET and SDH frequencies. Two independent clock generators provide the stan- dardized T0 and T4 functions. Each clock generator includes a DPLL (Digital Phase-Locked Loop), which may operate in the Freerun, Synchronized, and Hold- over modes. Both clock generators support master/ slave operation for redundant applications. Connor- Winfield’s proprietary SyncLinkTM Cross-couple data link provides master/slave phase information and state data to ensure seamless side switches. A standard SPI serial bus interface or parallel bus provide access to the STC4130’s comprehensive, yet simple to use internal control and status registers. The device operates with an external OCXO or TCXO as its MCLK at either 10 or 20 MHz. Features Functional Specification • For SDH SETS and SSU • For SONET Stratum 3E, 3, 4E, 4 and SMC • Complies with ITU-T G.812 Type III , G.813, Tel- cordia GR1244, and GR253 • Supports Master/Slave operation with the SyncLinkTM cross-couple data link for master/ slave redundant applications • Accepts 12 individual clock reference inputs • Reference clock inputs are automatically fre- quency detected • Supports manual or automatic reference selec- tion • T0 and T4 have independent reference lists and priority tables for automatic reference selection • 8 synchronized output clocks • Output/input phase skew is adjustable in slave mode, in 0.1nS steps up to 200nS • Hit-less reference and master/slave switching • Phase rebuild on re-lock and reference switches • Better than 0.1 ppb holdover accuracy • Programmable bandwidth, from 90mHz to 107Hz, for both T0 and T4 DPLL • Supports SPI or parallel bus interface • IEEE 1149.1 JTAG boundary scan • Available in TQ100 ROHS package T0_Master_Slave T0_Xsync_In Phase Detector Digital Filter 12 Reference Clk 8 KHz 64 KHz 1.544 MHz 2.048 MHz 19.44 MHz 38.88 MHz 77.76 MHz www.DataSheet4U.com T4_Xsync_In T4_Master_Slave OCXO TCXO 10MHz/ 20MHz T0 Active Ref Selector Activity & Frequency Offset Monitor T4 Active Ref Selector STC4130 To Clock Generator Phase Detector Digital Filter T4 Clock Generator Serial/Parallel Bus Interface Control & Status Registers IEE 1194.1 JTAG LVDS 155.52 MHz 19.44/38.88/77.76 MHz 19.44/38.88/77.76 MHz 8 KHz 2 KHz 1.544/3.088/6.176/12.352/24.704 MHz 2.048/4.096/8.192/16.384/32.768 MHZ 44.736 MHz/34.368 MHz T0_Xsync_Out 1.544 MHz/2.048 MHz T4_Xsync_Out Figure 1: Functional Block Diagram Data Sheet #: TM084 Page 1 of 44 Rev: P02 Date: 12/5/06 © Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 1 page Pin Name BUS_AD6 BUS_AD5 BUS_AD4 BUS_AD3 BUS_AD2 BUS_AD1 BUS_AD0 BUS_INTR REF1 REF2 REF3 REF4 REF5 REF6 REF7 REF8 REF9 REF10 REF11 REF12 T0_M/S T4_M/S T0_XSYNC_IN T0_XSYNC_OUT T4_XSYNC_IN T4_XSYNC_OUT CLK0_P CLK0_N CLK1 CLK2 CLK3 www.DataCShLKee4t4U.com CLK5 CLK6 CLK7 Test_Pin STC4130 Synchronous Clock for SETS Data Sheet Table 1: Pin Description Pin # 42 40 39 37 36 34 33 32 2 4 5 8 10 12 14 16 17 19 21 23 24 28 25 70 26 66 85 86 83 81 79 77 74 72 68 7,11,96 I/O1 Description I/O Parallel bus address/data bit6 I/O Parallel bus address/data bit5 I/O Parallel bus address/data bit4 I/O Parallel bus address/data bit3 I/O Parallel bus address/data bit2 I/O Parallel bus address/data bit1 I/O Parallel bus address/data bit0 O Interrupt I Reference input 1 I Reference input 2 I Reference input 3 I Reference input 4 I Reference input 5 I Reference input 6 I Reference input 7 I Reference input 8 I Reference input 9 I Reference input 10 I Reference input 11 I Reference input 12 I Select master or slave mode for T0, 1: Master, 0: Slave I Select master or slave mode for T4, 1: Master, 0: Slave I Cross-couple SyncLinkTM data link input fot T0 for master/slave redundant applications O Cross-couple SyncLinkTM data link output fot T0 for master/slave redundant applications I Cross-couple SyncLinkTM data link input fot T4 for master/slave redundant applications O Cross-couple SyncLinkTM data link output fot T4 for master/slave redundant applications O 155.52 MHz LVDS output O 155.52 MHz LVDS output O 19.44/38.88/77.76 MHz O 19.44/38.88/77.76 MHz O 8 KHz frame pulse or 50% duty cycle clock O 2 KHz frame pulse or 50% duty cycle clock O 44.736/34.368 MHz O 1.544/3.088/6.176/12.352/24.704/2.048/4.098/8.192/16.384/32.768 MHZ O 1.544/2.048 MHz I Test pin, must be grounded for normal operation Data Sheet #: TM084 Page 5 of 44 Rev: P02 Date: 12/5/06 © Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 5 Page beyond the disqualification range will disqualify the reference. It may then be re-qualified and the activity alarm is de-asserted, if it is within the qualification range for more than the qualification time. The reference qualification status of each reference may then be read from register Refs_Qual (0x1a/ 1b). Activity Alarm Asserted Activity Not Good Activity Alarm De-Asserted Activity Alarm Asserted STC4130 Synchronous Clock for SETS Data Sheet by writing bit 4 of the T0_Control_Mode (0x1c) or T4_Control_Mode (0x39) register (for T0 or T4, respectively) to 1. The reference is picked according to its indicated pri- ority in the reference priority table, Registers T0_Priority_Table (0x31~0x36) or T4_Priority_Table (0x4e ~ 0x0x53). Each reference has one entry in the table, which may be set to a value from 0 to 15. ‘0’ masks-out the reference, while 1 to 15 set the priority, where ‘1’ has the highest, and ‘15’ has the lowest priority. The highest priority pre- qualified reference is chosen as the active reference. The automatically selected reference for each DPLL may be read from registers T0_Auto_Active_Ref (0x1e) and T4_Auto_Active_Ref (0x3b). Within Offset Qualification Range for more than Qualification Time Activity Good Qualified Out of Disqualification Range The pre-qualification scheme is described in the Ref- erence Inputs Monitoring and Qualification sec- tion. When a selected active reference is disqualified, the highest priority qualified remaining reference is chosen. If multiple references share the same priority, they are ordered according to the dura- tion of their qualification. The longer the duration, the higher the priority is set. Figure 3: Reference Qualification and Disqualification DPLL Active Reference Selection The T0 and T4 clock generators may be individually operated in either manual or automatic input refer- ence selection mode. The mode is selected via the T0(4)_Control_Mode registers. Manual Reference Selection Mode In manual reference selection mode, the user may select the reference. Manual reference selection mode is selected by setting bit 4 of the T0_Control_Mode (0x1c) or T4_Control_Mode (0x39) register (for T0 or T4, respectively) to 0. The reference is selected by writing to bits 0 - 3 of the T0_Manual_Active_Ref (0x1f) and www.DaTta4S_hMeeat4nUu.acol_mActive_Ref (0x3c) registers. Automatic Reference Selection Mode In automatic reference selection mode, the device will select one pre-qualified reference as the active reference. Automatic reference selection mode is set When a reference is disqualified, and subsequently re-qualified as the highest priority candidate, it may or may not be re-selected as the active reference. This is determined by either enabling or disabling “reversion” by writing bit 3 of the T0_Control_Mode (0x1c) or T4_Control_Mode (0x39) register (for T0 or T4, respectively) to “1” for revertive or to “0” for non-revertive operation. If reversion is enabled, a qualified/re-qualified refer- ence will be selected as the new active reference, if it is the highest priority qualified reference at that time. If reversion is disabled, the active reference will not be pre-empted by a higher priority reference until it is disqualified. Digital Phase Locked Loop General Description The STC4130 includes both a T0 and T4 clock gen- erator. Each clock generator has a DPLL, including a phase detector and a digital filter. Each DPLL may select any of the 12 input reference clocks in master mode. In slave mode, they will Data Sheet #: TM084 Page 11 of 44 Rev: P02 Date: 12/5/06 © Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 11 Page

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