DataSheet39.com

What is GS880F36BT-7.5?

This electronic component, produced by the manufacturer "GSI Technology", performs the same function as "9Mb Sync Burst SRAMs".


GS880F36BT-7.5 Datasheet PDF - GSI Technology

Part Number GS880F36BT-7.5
Description 9Mb Sync Burst SRAMs
Manufacturers GSI Technology 
Logo GSI Technology Logo 


There is a preview and GS880F36BT-7.5 download ( pdf file ) link at the bottom of this page.





Total 27 Pages



Preview 1 page

No Preview Available ! GS880F36BT-7.5 datasheet, circuit

GS880F18/32/36BT-4.5/5/5.5/6.5/7.5
100-Pin TQFP
Commercial Temp
Industrial Temp
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
www.D4a.5taSnhsee7t4.5U.ncosm
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• Flow Through mode operation; Pin 14 = No Connect
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS880F18/32/36BT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with VSS connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Flow Through
2-1-1-1
Paramter Synopsis
-4.5 -5 -5.5 -6.5 -7.5 Unit
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
4.5 5.0 5.5 6.5 7.5 ns
4.5 5.0 5.5 6.5 7.5 ns
200 185 160 140 128 mA
230 210 185 160 145 mA
Rev: 1.02 10/2004
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

line_dark_gray
GS880F36BT-7.5 equivalent
TQFP Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
NC
BW
BA, BB, BC, BD
CK
GW
E1
G
ADV
ADSP, ADSC
ZZ
LBO
VDD
VSS
VDDQ
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
GS880F18/32/36BT-4.5/5/5.5/6.5/7.5
www.DataSheet4U.com
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte WriteWrites all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write EnableWrites all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.02 10/2004
5/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology


line_dark_gray

Preview 5 Page


Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for GS880F36BT-7.5 electronic component.


Information Total 27 Pages
Link URL [ Copy URL to Clipboard ]
Download [ GS880F36BT-7.5.PDF Datasheet ]

Share Link :

Electronic Components Distributor


An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists.


SparkFun Electronics Allied Electronics DigiKey Electronics Arrow Electronics
Mouser Electronics Adafruit Newark Chip One Stop


Featured Datasheets

Part NumberDescriptionMFRS
GS880F36BT-7.5The function is 9Mb Sync Burst SRAMs. GSI TechnologyGSI Technology

Semiconductors commonly used in industry:

1N4148   |   BAW56   |   1N5400   |   NE555   |  

LM324   |   BC327   |   IRF840  |   2N3904   |  



Quick jump to:

GS88     1N4     2N2     2SA     2SC     74H     BC     HCF     IRF     KA    

LA     LM     MC     NE     ST     STK     TDA     TL     UA    



Privacy Policy   |    Contact Us     |    New    |    Search