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What is GSC3E?

This electronic component, produced by the manufacturer "SiRF", performs the same function as "GPS Single Chip".


GSC3E Datasheet PDF - SiRF

Part Number GSC3E
Description GPS Single Chip
Manufacturers SiRF 
Logo SiRF Logo 


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Total 25 Pages



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GSC3e/LPx and GSC3f/LPx
High Performance, Lowest Power, GPS Single Chip
Datasheet
SiRFstarIII Architecture
PRODUCT DESCRIPTION
The GSC3e/LPx and GSC3f/LPx are the pin-for-pin
compatible, lowest power versions of the advanced
GSC3e(f)/LP receiver in a single package. The baseband
has been ported to 65 nm technology, enabling an
additional power reduction of up to 30 percent. In the
GSC3e/LPx, the baseband and RF are integrated into the
7 mm x 10 mm x 1.4 mm package. In the GSC3f/LPx,
flash memory is included in the package making for an
extremely compact design. The GSC3e(f)/LPx includes a
powerful GPS DSP integrated with an ARM7TDMI micro-
processor and 1 Mb of SRAM. The GSC3e(f)/LPx archi-
tecture uses an FFT and Matched Filter that delivers
performance equivalent to more than 200,000 corre-
lators. This represents a quantum leap forward in GPS
performance.
ARCHITECTURE HIGHLIGHTS
Next Generation, Lowest Power, GPS Performance
X 200,000+ effective correlators for fast TTFF
and high sensitivity acquisitions
X Supports 20-Channel GPS
X High sensitivity for indoor fixes
X Extremely fast TTFFs at low signal levels
X Real-time navigation for location-based services
X Low 100 ms interrupt load on microprocessor for easy
IP implementation
X SBAS (WAAS, MSAS, and EGNOS) support
SiRFLocTM Client AGPS Support
X SiRF patented end-to-end solution
X Multimodes: mobile centric to network centric
X Mutli-standard support: 3GPP, 3GPP2, PDC, iDEN,
and TIA-916
X Supports AI3 and F interfaces
GSW3—Modular Software Support
X API compatible with GSW2
X RTOS friendly
PRODUCT HIGHLIGHTS
GSC3f/LPx—Digital, RF, and Flash Single Chip
X Digital, RF, and 4 Mb Flash in a single package
X Small 7 mm x 10 mm x 1.4 mm, BGA package
X ARM7TDMI CPU and SRAM to enable user tasks
X Accepts six reference frequencies between 13 MHz
and 26 MHz
X Extensive GPS peripherals: 2 UARTs, battery-backed
SRAM, and 14 GPIOs
Lowest Power
X Under 60 mW at full power
X 46 mW tracking power
X Push-to-Fixreduces power as much as 98%
Built On Proven Experience
X IP integration experience
X Highly developed design tools
X FCC E911 compliance experience
GPS Antenna
LNA
RF Filter
RTCXTAL Reference
Clock
GSC3e/LPx
and
GSC3f/LPx
Serial Data
1 PPS
Reset
ECLK
(Optional)
Serial Data
Power
Battery
Figure 1. Sample Architecture Diagram
Preliminary Datasheet S SiRF Proprietary and Confidential S 1055-1061 May 2009 S www.sirf.com
www.DataSheet.in

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GSC3E equivalent
GSC3e/LPx and GSC3f/LPx: High Performance, Lowest Power, GPS Single Chip
CLOCK MODULE
This module generates all internal clocks such as the
Signal Processing (SP) Clock and Bus (B) Clock from
the Acquisition Clock. The Acquisition Clock is
generated by the RF section. The clocks generated by
Clock Module run the SiRFstarIII DSP and ARM and
control the various power management modes allowing
for maximum power savings and system flexibility.
DUART
The GSC3e(f)/LPx contains two full duplex serial ports.
One port is normally used for GPS data and receiver
control and the second serial port can be used as an
alternate communication channel. The transmit and
receive side of each port contains a 16-byte deep FIFO
with selectable bit rates ranging from 1.2 to 115.2
Kbaud. With special flashing software, maximum baud
rate of 921.6 kbps is available.
GPIO UNIT
The GSC3e(f)/LPx supports a variety of peripherals
through 14 GPIO lines. The GPIO unit centralizes
management of all GPIO lines and provides a simple
software interface for their control.
FLASH
The GSC3f/LPx integrates 4 Mbits of Flash memory.
This eliminates the need for external Flash and signifi-
cantly simplifies the routing associated with integrating
a GPS receiver into a board design. This chip is not
available in a pre-flashed version.
INTERRUPT CONTROLLER
The Interrupt Controller manages all internal or external
sources of interrupts. These include the SiRFstarIII
core, SBAS, DSP, DUART and external user interrupts.
SIRF BRIDGE UNIT
The SiRF Bridge Units (SBU1 and SBU2) provide low
power access to peripherals. SBU1 provides access to
general purpose ARM peripherals such as the serial
port UARTS, RTC, and interrupt controller. SBU2
provides access to the DSP core and its associated
memory. The DSP core also uses this bus for internal
communications. The ARM is able to perform byte,
half-word, and word transactions via the 32-bit
peripheral busses.
SRAM
The on-chip SRAM size is 1 Mbit (32k x 32) memory
that can be used for instructions or data. In many
applications it eliminates the need for external data
memory. The SRAM is designed for a combination of
low power and high speed, and can support single
cycle reads for all bus speeds.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) port handles
communication, such as reference frequency selection,
AGC, and power control, between the digital and RF
sections. The RF section acts in slave mode and can
only be controlled by the digital section using SiRF
software. The SPI port consists of SPI_CLK, SPI_DI,
SPI_DO, and SPI_CEB for the RF section, and corre-
sponds to SK, SI, SO, and CEB in the digital section.
The SPI port does not support additional SPI devices. It
is only used for internal communication between RF
and BB.
DSP RAM AND RAM SHARING
The GSC3e(f)/LP includes shared RAM which is
allocated between ARM and DSP core. This keeps the
overall size of the chip down while maximizing the
availability of memory.
FACTORY TESTING
The GSC3e(f)/LPx uses a memory built-in self-test
called MEMBIST to provide complete coverage of all
the memory during chip testing and qualification. This
is combined with the SCAN test logic using Automatic
Test Pattern Generation (ATPG) at the wafer level to
provide functional test coverage. (These functions are
not available to customers.)
Preliminary Datasheet S SiRF Proprietary and Confidential S 1055-1061 May 2009 S www.sirf.com
www.DataSheet.in
page 5


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for GSC3E electronic component.


Information Total 25 Pages
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