|
|
PDF 73S1209F Data sheet ( Hoja de datos )
| Número de pieza | 73S1209F | |
| Descripción | Smart Card Reader IC UART to ISO7816 / EMV Bridge IC | |
| Fabricantes | Teridian Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 73S1209F (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
73S1209F
Self-Contained PINpad, Smart Card Reader
IC UART to ISO7816 / EMV Bridge IC
Simplifying System Integration™
DATA SHEET
December 2008
GENERAL DESCRIPTION
The Teridian Semiconductor Corporation 73S1209F is a
versatile and economical CMOS System-on-Chip device
intended for smart card reader applications. More
generally, it is suitable anywhere a UART to ISO-7816 /
EMV bridge function is needed. The circuit is built around
an 80515 high-performance core; it features primarily an
ISO-7816 / EMV interface and a generic asynchronous
serial interface. Delivered with turnkey Teridian embedded
firmware, it forms a ready-to-use smart card reader solution
that can be seamlessly incorporated into any
microprocessor-based system where a serial line is
available.
The solution is scalable, thanks to a built-in I2C interface
that allows to drive external electrical smart card interfaces
such as Teridian 73S8010R/C ICs. This makes the solution
immediately able to support multi-card slots or multi-SAM
architectures.
In addition, the 73S1209F features a 5x6 PINpad interface,
9 user I/Os, 2 LED outputs (programmable current),
multiple interrupt options and an analog voltage input (for
DC voltage monitoring such as battery level detection) that
make it suitable for low-cost PINpad reader devices.
The 80515 CPU core instruction set is compatible with the
industry standard 8051, while offering one clock-cycle per
instruction processing power (most instructions). With a
CPU clock running up to 24MHz, it results in up to 24MIPS
available that meets the requirements of various encryption
needs such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance).
The circuit requires a single 6MHz to 12MHz crystal.
The respective 73S1209F embedded memories are 32KB
Flash program memory, 2KB user XRAM memory, and
256B IRAM memory. Dedicated FIFOs for the ISO7816
UART are independent from the user XRAM and IRAM.
Alternatively to the turnkey firmware offered by Teridian,
customers can develop their own embedded firmware
directly within their application or using Teridian 73S1209F
Evaluation Board through a JTAG-like interface.
Overall, the Teridian 73S1209F IC requires 2 distinct power
supply voltages to operate normally with full support of all
smart card voltages, 1.8V, 3V and 5V. The digital power
supply VDD requires a 2.7V to 3.6V voltage, and the analog
power supply VPC requires typically a 4.75V to 6.0V.
While the VDD is used to power up the CPU core and the
digital functions of the IC, the VPC voltage is used to supply
the proper VCC voltage to the smart card interface: The chip
incorporates an low drop-out linear voltage regulator that
generates the smart card power-supply VCC from the power
supply source VPC.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the 73S1209F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1209F a very comprehensive set of software
libraries for EMV. Refer to the 73S12xxF Software
User’s Guide for a complete description of the
Application Programming Interface (API Libraries) and
related Software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable rapid
development and certification of readers that meet
most demanding smart card standards.
APPLICATIONS
• UART to ISO-7816 / EMV Bridges
• PINpad smart card readers:
o With serial connectivity
o Ideal for low-cost POS Terminals) & Digital
Identification (Secure Login, Gov’t ID...)
• SIM Readers in Telecom & Personal Wireless
devices
• Payphones and vending machines
• General purpose smart card readers
ADVANTAGES
• Reduced BOM
• Low-Cost
• Dual power supply required 3.3V and 5V
typical
• Higher performance CPU core (up to 24MIPS)
• Built-in EMV/ISO slot, expandable to multi-
slots
• Powerful In-Circuit Emulation and
Programming
• A complete set of EMV4.1 / ISO-7816
libraries
• Turnkey PC/SC and CCID firmware and host
drivers
o Supported OS: Windows XP, WindowsTM
Mobile; Windows CE; Linux
o Other OS: Contact Teridian Semiconductor
Rev. 1.2
© 2008 Teridian Semiconductor Corporation
1
1 page  
DS_1209F_004
73S1209wFwDwa.DtaataSShheeete4Ut .com
Tables
Table 1: 73S1209F Pinout Description ......................................................................................................... 8
Table 2: MPU Data Memory Map................................................................................................................ 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Security Control Registers ............................................................................................................ 17
Table 6: IRAM Special Function Registers Locations................................................................................. 18
Table 7: IRAM Special Function Registers Reset Values........................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 21
Table 9: PSW Register Flags...................................................................................................................... 22
Table 10: Port Registers ............................................................................................................................. 23
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 25
Table 12: The MCLKCtl Register ................................................................................................................ 25
Table 13: The MPUCKCtl Register ............................................................................................................. 26
Table 14: The INT5Ctl Register .................................................................................................................. 29
Table 15: The MISCtl0 Register.................................................................................................................. 29
Table 16: The MISCtl1 Register.................................................................................................................. 30
Table 17: The MCLKCtl Register ................................................................................................................ 30
Table 18: The PCON Register .................................................................................................................... 31
Table 19: The IEN0 Register....................................................................................................................... 33
Table 20: The IEN1 Register....................................................................................................................... 34
Table 21: The IEN2 Register....................................................................................................................... 34
Table 22: The TCON Register .................................................................................................................... 35
Table 23: The T2CON Register .................................................................................................................. 35
Table 24: The IRCON Register ................................................................................................................... 36
Table 25: External MPU Interrupts.............................................................................................................. 36
Table 26: Control Bits for External Interrupts.............................................................................................. 37
Table 27: Priority Level Groups................................................................................................................... 37
Table 28: The IP0 Register ......................................................................................................................... 37
Table 29: The IP1 Register ......................................................................................................................... 38
Table 30: Priority Levels.............................................................................................................................. 38
Table 31: Interrupt Polling Sequence.......................................................................................................... 38
Table 32: Interrupt Vectors.......................................................................................................................... 38
Table 33: UART Modes............................................................................................................................... 39
Table 34: Baud Rate Generation ................................................................................................................ 39
Table 35: The PCON Register .................................................................................................................... 40
Table 36: The BRCON Register ................................................................................................................. 40
Table 37: The MISCtl0 Register.................................................................................................................. 41
Table 38: The S0CON Register .................................................................................................................. 42
Table 39: The S1CON Register .................................................................................................................. 43
Table 40: The TMOD Register .................................................................................................................... 44
Table 41: TMOD Register Bit Description................................................................................................... 44
Table 42: Timers/Counters Mode Description ............................................................................................ 45
Table 43: The TCON Register .................................................................................................................... 46
Table 44: The IEN0 Register....................................................................................................................... 47
Table 45: The IEN1 Register....................................................................................................................... 47
Table 46: The IP0 Register ......................................................................................................................... 48
Table 47: The WDTREL Register ............................................................................................................... 48
Table 48: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49
Table 49: UDIR Control Bit.......................................................................................................................... 49
Table 50: Selectable Controls Using the UxIS Bits..................................................................................... 49
Table 51: The USRIntCtl1 Register ............................................................................................................ 50
Table 52: The USRIntCtl2 Register ............................................................................................................ 50
Table 53: The USRIntCtl3 Register ............................................................................................................ 50
Table 54: The USRIntCtl4 Register ............................................................................................................ 50
Table 55: The ACOMP Register ................................................................................................................. 51
Table 56: The INT6Ctl Register .................................................................................................................. 52
Rev. 1.2
5
5 Page 
DS_1209F_004
73S1209wFwDwa.DtaataSShheeete4Ut .com
1.2 Hardware Overview
The 73S1209F single smart card controller integrates all primary functional blocks required to implement
a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up
to one instruction per clock cycle (80515), a fully integrated IS0-7816 compliant smart card interface,
expansion smart card interface, serial interface, I2C interface, 6 x 5 keypad interface, 2 LED drivers,
RAM, FLASH memory, and a variety of I/O pins. A functional block diagram of the 73S1209F is shown in
Figure 1.
1.3 80515 MPU Core
1.3.1 80515 Overview
The 73S1209F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one
clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution
of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most
of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application
(cryptographic calculations, key management, memory management, and I/O management) using the
XRAM special function register MPUCKCtl.
Typical smart card, serial, keyboard and I2C management functions are available for the MPU as part of
Teridian’s standard library. A standard ANSI “C” 80515-application programming interface library is
available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.
1.3.2 Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three
memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory
(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2
Table 2: MPU Data Memory Map
Address
(hex)
0000-7FFF
0000-07FF
FC00-FFFF
Memory
Technology
Flash Memory
Static RAM
External SFR
Memory Type
Non-volatile
Volatile
Volatile
Typical Usage
Program and non-volatile data
MPU data XRAM
Peripheral control
Note: The IRAM is part of the core and is addressed differently.
Memory Size
(bytes)
32KB
2KB
1KB
Program Memory: The 80515 can address up to 32KB of program memory space from 0x0000 to
0x7FFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program
memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting
from 0x0003. Reset is located at 0x0000.
Flash Memory: The program memory consists of flash memory. The flash memory is intended to
primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to
specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent
inadvertent erasure of the flash memory.
Rev. 1.2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 73S1209F.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 73S1209F | Smart Card Reader IC UART to ISO7816 / EMV Bridge IC | Teridian Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |