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What is IDT72P51559?

This electronic component, produced by the manufacturer "Integrated Device Technology", performs the same function as "1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION".


IDT72P51559 Datasheet PDF - Integrated Device Technology

Part Number IDT72P51559
Description 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION
Manufacturers Integrated Device Technology 
Logo Integrated Device Technology Logo 


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1.8V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION
589,824 bits
1,179,648 bits
2,359,296 bits
4,718,592 bits
ADVANCE INFORMATION
www.DIDaTta7S2hPe5e1t54U3.9com
IDT72P51549
IDT72P51559
IDT72P51569
FEATURES
Choose from among the following memory density options:
IDT72P51539 Total Available Memory = 589,824 bits
IDT72P51549 Total Available Memory = 1,179,648 bits
IDT72P51559 Total Available Memory = 2,359,296 bits
IDT72P51569 Total Available Memory = 4,718,592 bits
Configurable from 1 to 32 Queues
Default configuration of 32 or 16 symmetrical queues
Default multi-queue device configurations
– IDT72P51539: 512 x 36 x 32Q
– IDT72P51549: 1,024 x 36 x 32Q
– IDT72P51559: 2,048 x 36 x 32Q
– IDT72P51569: 4,096 x 36 x 32Q
Default configuration can be augmented via the queue address
bus
Number of queues and individual queue sizes may be
configured at master reset though serial programming
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Independent Read and Write access per queue
User Selectable Bus Matching Options:
– x36 in to x36 out – x18 in to x36 out
– x9 in to x36 out
– x36in to x18out
– x18 in to x18 out
– x9 in to x18 out
– x36in to x9out
– x18 in to x9 out
– x9 in to x9 out
User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL
100% Bus Utilization, Read and Write on every clock cycle
Selectable First Word Fall Through (FWFT) or IDT standard
mode of operation
Ability to operate on packet or word boundaries
Mark and Re-Write operation
Mark and Re-Read operation
Individual, Active queue flags (OR / EF, IR / FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Direct or polled operation of flag status bus
Expansion of up to 256 queues and/or 32Mb logical configura-
tion using up to 8 multi-queue devices in parallel
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
WRADD
WEN 8
WCLK
WCS
Din
x36, 18 or x9
DATA IN
FF/IR
PAF
PAFn
8
Q31
Q30
Q29
Q0
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RADEN
ESTR
RDADD
8 REN
RCLK
RCS
OE
Qout
x36, x18 or x9
DATA OUT
EF/OR
PR
PAE
PAEn
8 PRn
6715 drw01
SEPTEMBER 2004
DSC-6715/-

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IDT72P51559 equivalent
IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DESCRIPTION
The IDT72P51539/72P51549/72P51559/72P51569 multi-queue flow-con-
trol devices are single chips with up to 32 discrete configurable FIFO queues.
All queues within the device have a common data input bus, (write port) and
a common data output bus, (read port). Data written into the write port is directed
to a specific queue via an internal de-multiplex operation, addressed by the write
address bus (WRADD). Data read from the read port is accessed from a specific
queue via an internal multiplex operation, addressed by the read address bus
(RDADD). Data writes and reads can be performed at high speeds up to
200MHz, with access times of 3.6ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and a
different queue on the read port or both ports may select the same queue
simultaneously.
The device provides Full flag and Empty flag status for the queue selected
for write and read operations respectively. Also a Programmable Almost Full
and Programmable Almost Empty flag for each queue is provided. Two 8 bit
programmable flag busses are available, providing status of queues not
selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when more
than 8 queues are used, either a Polled or Direct mode bus operation provides
the flag busses with all queues status.
Bus Matching is available on this device, either port can be 9 bits, 18 bits or
36 bits wide. When Bus Matching is used the device ensures the logical transfer
of data throughput in a Little Endian manner.
A packet mode of operation is also provided. Packet mode provides a packet
ready flag output (PR) indicating when at least one (or more) packets of data
within a queue is available for reading. The Packet Ready indicator is generated
upon detection of the start and end of packet demarcatiwonwbwits.D. TahteamShuletie-qtu4eUu.ce om
device then provides the user with an internally generated packet ready status
per queue.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
A Master Reset must be provided to the device. A Master Reset latches in
configuration/setup pins and must be performed before further programming of
the device can take place. On the rising edge of master reset the device operating
mode is set, the device programming mode (serial, parallel or default) is set and
the expansion configuration device type (master or slave) is set.
The multi-queue flow-control device has the capability of operating its I/O in
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of I/O is selected
via the IOSEL input. The core supply voltage (VDD) to the multi-queue is 1.8V,
however the output levels can be set independently via a separate supply,
VDDQ.
A JTAG test port is provided, here the multi-queue flow-control device has
a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an
outline of the functional blocks within the device.
5 SEPTEMBER 27, 2004


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Featured Datasheets

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IDT72P51559The function is 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION. Integrated Device TechnologyIntegrated Device Technology

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