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PDF 74LVC2G74 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G74 | |
| Descripción | Single D-type flip-flop | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVC2G74
www.DataSheet4U.com
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 06 — 23 December 2009
Product data sheet
1. General description
The 74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant inputs for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ±24 mA output drive (VCC = 3.0 V)
I ESD protection:
N HBM JESD22-A114F exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page  
NXP Semiconductors
74LVC2G74
www.DataSheet4U.com
Single D-type flip-flop with set and reset; positive edge trigger
Table 5.
Input
SD
H
H
Function table for synchronous operation[1]
RD CP
H↑
H↑
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
D
L
H
8. Limiting values
Output
Qn+1
L
H
Qn+1
H
L
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current
VI input voltage
IOK output clamping current
VO output voltage
VI < 0 V
VO > VCC or VO < 0 V
Active mode
Power-down mode
−0.5
−50
[1] −0.5
-
[1][2] −0.5
[1][2] −0.5
+6.5 V
- mA
+6.5 V
±50 mA
VCC + 0.5 V
+6.5 V
IO
ICC
IGND
Ptot
Tstg
output current
supply current
ground current
total power dissipation
storage temperature
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
-
-
−100
[3] -
−65
±50
100
-
300
+150
mA
mA
mA
mW
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
VI
VO
Operating conditions
Parameter
supply voltage
input voltage
output voltage
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
Conditions
Active mode
Power-down mode; VCC = 0 V
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
Min
1.65
0
0
0
−40
-
-
Max
5.5
5.5
VCC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC2G74_6
Product data sheet
Rev. 06 — 23 December 2009
© NXP B.V. 2009. All rights reserved.
5 of 21
5 Page 
NXP Semiconductors
74LVC2G74
www.DataSheet4U.com
Single D-type flip-flop with set and reset; positive edge trigger
VI
CP input
GND
VI
SD input
GND
VI
RD input
GND
VOH
Q output
VOL
VOH
Q output
VOL
VM
tW
t PLH
VM
VM
t PHL
VM
t rec
tW
VM
t PHL
t rec
t PLH
mnb142
Fig 9.
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and
the RD to CP recovery time
74LVC2G74_6
Product data sheet
Rev. 06 — 23 December 2009
© NXP B.V. 2009. All rights reserved.
11 of 21
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