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PDF UL62H256A Data sheet ( Hoja de datos )
| Número de pieza | UL62H256A | |
| Descripción | Low Voltage Automotive Fast 32K x 8 SRAM | |
| Fabricantes | Zentrum Mikroelektronik Dresden AG | |
| Logotipo |  |
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UL62H256A
Low Voltage Automotive Fast 32K x 8 SRAM
Features
Description
! 32768 x 8 bit static CMOS RAM
! 35 and 55 ns Access Time
! Common data inputs and
data outputs
! Three-state outputs
! Typ. operating supply current
35 ns: 45 mA
55 ns: 30 mA
! Standby current < 40 µA at 125 °C
! TTL/CMOS-compatible
! Power supply voltage 2.5 - 3.6 V
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-40 °C to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity >100 mA
! Package: SOP28 (300/330 mil)
The UL62H256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word will be available at the
outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
is available. The data outputs have
no preferred state. The Read cycle
is finished by the falling edge of W,
or by the rising edge of E, respec-
tively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 SOP 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
May 07, 2004
Pin Description
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply
Voltage
Ground
1
1 page  
UL62H256A
Switching Characteristics
Read Cycle
Symbol
Alt. IEC
Read Cycle Time
tRC
Address Access Time to Data Valid
tAA
Chip Enable Access Time to Data Valid
tACE
G LOW to Data Valid
tOE
E HIGH to Output in High-Z
tHZCE
G HIGH to Output in High-Z
tHZOE
www.DataSheet4U.com
E LOW to Output in Low-Z
tLZCE
G LOW to Output in Low-Z
tLZOE
Output Hold Time from Address Change
tOH
E LOW to Power-Up Time
tPU
E HIGH to Power-Down Time
tPD
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
35
Min.
Max.
35
35
35
15
12
12
3
0
3
0
35
55
Min.
Max.
55
55
55
25
15
15
3
0
3
0
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Setup Time
Address Setup Time
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
Data Hold Time
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
Symbol
Alt.
tWC
tWP
tWP
tAS
tAW
tCW
tCW
tDS
tDH
tAH
tHZWE
tHZOE
tLZWE
tLZOE
IEC
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
tsu(D)
th(D)
th(A)
tdis(W)
tdis(G)
ten(W)
ten(G)
35
Min.
Max.
35
20
20
0
25
25
25
15
0
0
15
12
0
0
55
Min.
Max.
55
35
35
0
40
40
40
25
0
0
20
15
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
May 07, 2004
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UL62H256A.PDF ] | |
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