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What is GS8662Q18E-250?

This electronic component, produced by the manufacturer "GSI Technology", performs the same function as "72Mb SigmaQuad-II Burst".


GS8662Q18E-250 Datasheet PDF - GSI Technology

Part Number GS8662Q18E-250
Description 72Mb SigmaQuad-II Burst
Manufacturers GSI Technology 
Logo GSI Technology Logo 


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Total 35 Pages



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165-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
GS8662Q08/09/18w/3w6wE.D-3at0a0Sh/2ee5t04U/2.c0o0m/167
72Mb SigmaQuad-II
Burst of 2 SRAM
300 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, and 36Mb and
future 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GSQ8662Q08/09/18/36E are built in compliance with
the SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B2 RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read or
write transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a SigmaQuad-II B2 RAM is always one address pin
less than the advertised index depth (e.g., the 4M x 18 has a
2048K addressable index).
Parameter Synopsis
tKHKH
tKHQV
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.01 9/2005
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology

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GS8662Q18E-250 equivalent
Preliminary
GS8662Q08/09/18/36E-300/250/200/167
www.DataSheet4U.com
8M x 9 SigmaQuad-II SRAM — Top View
123456789
A CQ SA SA W NC K NC R SA
B NC NC NC SA NC K BW SA NC
C NC NC NC VSS SA SA SA VSS NC
D NC D5 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS VDDQ
NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D8 NC VSS SA SA SA VSS NC
P NC NC Q8 SA SA C SA SA NC
R TDO TCK
Note: MCL = Must Connect Low
SA SA SA C SA SA SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
10
SA
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Rev: 1.01 9/2005
5/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology


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Part NumberDescriptionMFRS
GS8662Q18E-250The function is 72Mb SigmaQuad-II Burst. GSI TechnologyGSI Technology

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