GS8662S08E-200 Datasheet PDF - GSI Technology
Part Number | GS8662S08E-200 | |
Description | DDR SigmaSIO-II SRAM | |
Manufacturers | GSI Technology | |
Logo | ||
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GS8662S08/09/18/36E-333/300/250/200/167
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165-Bump BGA
Commercial Temp
Industrial Temp
72Mb Burst of 2
DDR SigmaSIO-II SRAM
333 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with future 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaRAM™ Family Overview
GS8662S08/09/18/36 are built in compliance with the
SigmaSIO-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 4M x 18 has a 1M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
- 333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.01 9/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
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Preliminary
GS8662S08/09/18/36Ew-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/167
2M x 36 SigmaQuad SRAM—Top View
1 2 3 4 5 6 7 8 9 10
A
CQ
VSS/SA
(288Mb)
SA
R/W BW2
K
BW1 LD
SA
VSS/SA
(144Mb)
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17
C D27 Q28 D19 VSS SA SA SA VSS D16 Q7
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
G
D30
D22
Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
D13
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
K
Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
D3
L
Q33
Q24
D24 VDDQ VSS
VSS
VSS
VDDQ
D11
Q11
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
N
D34 D26 Q25 VSS SA
SA
SA
VSS Q10
D9
P
Q35 D35 Q26
SA
SA
C
SA SA Q9 D0
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.
3. It is recommended that H1 be tied low for compatibility with future devices.
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.01 9/2005
5/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
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