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PDF 74AUP1G373 Data sheet ( Hoja de datos )
| Número de pieza | 74AUP1G373 | |
| Descripción | Low-power D-type transparent latch 3-state | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74AUP1G373
www.DataSheet4U.com
Low-power D-type transparent latch; 3-state
Rev. 03 — 9 January 2008
Product data sheet
1. General description
The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While
the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is
LOW, the latch stores the information that was present at the D-input one set-up time
preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of
the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the
high-impedance OFF-state. Operation of input pin OE does not affect the state of the
latch.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114E Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page  
NXP Semiconductors
74AUP1G373www.DataSheet4U.com
Low-power D-type transparent latch; 3-state
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
VOH HIGH-level output voltage
VOL LOW-level output voltage
II input leakage current
IOZ OFF-state output current
IOFF
∆IOFF
ICC
power-off leakage current
additional power-off
leakage current
supply current
∆ICC
additional supply current
CI input capacitance
CO output capacitance
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage
VIL LOW-level input voltage
VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
VCC = 0 V to 3.6 V; VI = GND or VCC
output enabled; VO = GND; VCC = 0 V
output disabled; VCC = 0 V to 3.6 V;
VO = GND or VCC
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC − 0.1 -
0.75 × VCC -
1.11 -
1.32 -
2.05 -
1.9 -
2.72 -
2.6 -
--
--
--
--
--
--
--
--
--
--
--
--
--
[1] -
-
- 0.8
- 1.7
- 1.5
0.70 × VCC -
0.65 × VCC -
1.6 -
2.0 -
--
--
--
--
Max Unit
-V
-V
-V
-V
-V
-V
-V
-V
0.1
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.1
V
V
V
V
V
V
V
V
µA
µA
±0.2 µA
±0.2 µA
0.5 µA
40 µA
- pF
- pF
- pF
-V
-V
-V
-V
0.30 × VCC V
0.35 × VCC V
0.7 V
0.9 V
74AUP1G373_3
Product data sheet
Rev. 03 — 9 January 2008
© NXP B.V. 2008. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
74AUP1G373www.DataSheet4U.com
Low-power D-type transparent latch; 3-state
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min Max Min
Max
(85 °C) (85 °C) (125 °C) (125 °C)
CL = 30 pF
tpd propagation D to Q; see Figure 7
delay
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
LE to Q; see Figure 8
[2]
-
4.0
3.6
3.5
3.3
3.0
[2]
35.9 -
10.6 22.1
7.5 12.3
6.2 9.5
5.1 6.9
4.7 6.4
-
3.7
3.5
3.2
2.9
2.9
-
23.3
13.6
10.5
7.6
7.2
-
3.7
3.5
3.2
2.9
2.9
- ns
25.6 ns
15.0 ns
11.5 ns
8.3 ns
7.9 ns
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
ten enable time OE to Q; see Figure 10
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
tdis disable time OE to Q; see Figure 10
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 5 pF, 10 pF, 15 pF and 30 pF
tW pulse width LE HIGH; see Figure 8
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
-
3.9
3.5
3.3
3.1
2.9
[3]
-
5.5
4.6
4.2
3.6
3.4
[4]
-
8.0
6.3
7.3
5.2
7.5
34.8 -
10.2 22.2
7.2 12.4
5.9 9.5
4.8 6.8
4.4 6.1
34.5 -
9.1 16.2
6.7 9.9
5.7 7.9
4.9 6.4
4.7 6.1
19.2 -
9.9 13.7
7.7 9.7
8.7 10.6
6.2 7.5
8.8 10.2
-
3.7
3.4
3.0
2.7
2.6
-
4.9
4.2
3.7
3.4
3.3
-
7.9
6.2
7.2
5.1
7.4
-
23.5
13.7
10.5
7.5
7.0
-
16.2
10.5
8.6
6.9
6.5
-
14.5
10.5
11.3
7.8
10.5
-
3.7
3.4
3.0
2.7
2.6
-
4.9
4.2
3.7
3.4
3.3
-
7.9
6.2
7.2
5.1
7.4
- ns
25.9 ns
15.1 ns
11.6 ns
8.2 ns
7.7 ns
- ns
17.8 ns
11.6 ns
9.5 ns
7.6 ns
7.2 ns
- ns
16.0 ns
11.6 ns
12.4 ns
8.6 ns
11.6 ns
- 4.0 -
- 0.7 -
- 0.5 -
- 0.4 -
- 0.3 -
- 0.2 -
-
2.1
1.3
1.0
0.8
0.8
-
-
-
-
-
-
-
2.1
1.3
1.0
0.8
0.8
- ns
- ns
- ns
- ns
- ns
- ns
74AUP1G373_3
Product data sheet
Rev. 03 — 9 January 2008
© NXP B.V. 2008. All rights reserved.
11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 74AUP1G373.PDF ] | |
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