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PDF UPD160970 Data sheet ( Hoja de datos )
| Número de pieza | UPD160970 | |
| Descripción | 8-ch level shift driver IC | |
| Fabricantes | NEC | |
| Logotipo |  |
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PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
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µ PD160970
8-ch level shift driver IC
DESCRIPTION
The µ PD160970 is a level shift driver IC for LTPS (low-temperature polysilicon) TFT-LCDs featuring a 2-level output
function and incorporates eight on-chip level shifters. This IC realizes a 20 V MAX. withstanding voltage due to a
high-withstanding-voltage CMOS process and has an output ON-resistance and switching characteristics ideal for
TFT driving in LCD panels.
FEATURES
• High withstanding voltage : 20 V (MAX.)
• Supports low-voltage input (logic power supply voltage : 3.0 to 3.6 V)
• Includes 8 level shifters (among which 2 circuits can switch between normal and inverted output)
• Small thin package : 24-pin plastic TSSOP (5.72 mm (225) )
ORDERING INFORMATION
Part Number
µ PD160970MA-6A5
Package
24-pin plastic TSSOP (5.72 mm (225) )
.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15857EJ4V0PM00 (4th edition)
Date Published January 2003 NS CP (K)
Printed in Japan
The mark 5 shows major revised points.
2003
1 page  
µ PD160970
5. ELECTRICAL SPECIFICATIONS
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Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Symbol
Logic Part Supply Voltage
VDD
Positive power supply for high
-withstanding-voltage block
Negative power supply for high
-withstanding-voltage block
Bias power supply for high
-withstanding-voltage block
Input Voltage
VCC
VEE
VCC -VEE
VI
Output Voltage
VO
Operating Ambient Temperature TA
Storage Temperature
Tstg
Power Dissipation
Pd
Rating
−0.5 to +4.5
−0.5 to +17.0
−8.0 to +0.5
−0.5 to +25.0
−0.5 to VDD + 0.5
VEE − 0.5 to VCC + 0.5
−10 to +60
−40 to +125
500Note
Note When a glass epoxy board (100 mm x 100 mm x 1.0 mm, copper-plated area of 15%) is mounted.
Unit
V
V
V
V
V
V
°C
°C
mW
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = −10 to +60°C, VSS = 0 V)
Parameter
Symbol
Conditions
Supply Voltage
VDD
Clock Frequency
VCC
VEE
VCC -VEE
fCLK
MIN.
3.0
9.5
−6.5
14.0
TYP.
3.3
11.5
−5.5
17.0
MAX.
3.6
13.5
−4.5
20.0
200
Unit
V
V
V
V
kHz
Electrical Characteristics (TA = −10 to +60°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V, VCC = 11.5 V ± 1.0 V, VEE = −5.5 V ±
0.5 V, tr = tf ≤ 5.0 ns)
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Low-Level Input Voltage
VIL
High-Level Input Voltage
VIH
Low-Level Output Voltage VOL
High-Level Output Voltage VOH
Output ON Resistance
RON
Static Current
IDD
ICC
Input Leak Current
IIL
5 Input Capacitance
CI
All input pins
All input pins
IOL = +1.0 mA, All output pins
IOH = −1.0 mA, All output pins
IO = ±1.0 mA, All output pins
VI = VSS
VDD
no load
VCC
VI = VDD or VSS, All input pins
VSS
0.7 VDD
10.37
−1.0
−5.42
11.42
80
0.1
0.1
7
0.2 VDD
VDD
−4.87
130
10
10
1.0
V
V
V
V
Ω
µA
µA
µA
pF
Note The TYP. value is a reference value when TA = 25°C, VDD = 3.3 V, VCC = 11.5 V, VEE = −5.5 V.
Preliminary Product Information S15857EJ4V0PM
5
5 Page 
µ PD160970
NOTES FOR CMOS DEVICES
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1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Product Information S15857EJ4V0PM
11
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