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What is UPD160040B?

This electronic component, produced by the manufacturer "NEC", performs the same function as "384-OUTPUT TFT-LCD SOURCE DRIVER".


UPD160040B Datasheet PDF - NEC

Part Number UPD160040B
Description 384-OUTPUT TFT-LCD SOURCE DRIVER
Manufacturers NEC 
Logo NEC Logo 


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DATA SHEET
www.DataSheet4U.com
MOS INTEGRATED CIRCUIT
µPD160040B
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256-GRAY SCALE)
DESCRIPTION
The µPD160040B is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scale. Data input
is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216
colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules.
Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray-scale voltage of differing polarity.
FEATURES
CMOS level input
384 outputs
Input of 8 bits (gray scale data) by 6 dots
Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter
Logic power supply voltage (VDD1): 2.5 to 3.6 V
Driver power supply voltage (VDD2): 12.5 to 15.5 V (switchable, VSEL)
Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
High-speed data transfer: fCLK. = 55 MHz MAX. (internal data transfer speed when operating at 3.0 V VDD1 3.6 V)
fCLK. = 40 MHz MAX. (internal data transfer speed when operating at 2.5 V VDD1 < 3.0 V)
Apply for dot-line inversion, n-line inversion and column line inversion
Output voltage polarity inversion function (POL)
Output inversion function (POL21, POL 22)
Output reset control is possible (MODE)
Trough-rate control is possible (SRC)
Output resistance control is possible (ORC)
Single bank arrangement is possible (Loaded with slim TCP)
ORDERING INFORMATION
Part Number
µPD160040BN-xxx
Package
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15953EJ2V0DS00 (2nd edition)
Date Published January 2003 NS CP (K)
Printed in Japan
The mark 5 shows major revised points.
2001

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UPD160040B equivalent
µPD160040B
Pin Symbol
MODE
POL21,
POL22
VSEL
V0-V15
TEST
VDD1
VDD2
VSS1
VSS2
Pin Name
Output reset control
Data inversion
Driver voltage select
γ -corrected power supplies
Test
Logic power supply
Driver power supply
Logic ground
Driver ground
I/O
Input
Input
Input
Input
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(2/2)
Description
MODE = H or open: Output reset
MODE = L: No output reset
MODE is pulled up to the VDD1 in the IC.
Select of inversion or no inversion for input data.
POL21: Data inversion or no inversion of Port1.
POL22: Data inversion or no inversion of Port2
POL21, POL22 = H: Data are inverted in the IC.
POL21, POL22 = L: Data are not inverted in the IC.
The driver voltage can be switched by controlling the stationary bias
current of the output amplifier via VSEL.
VSEL = H: VDD2 = 12.5 to (14.0 V) (large bias current)
VSEL = L or open: VDD2 = (14.0 V) to 15.5 V (small bias current)
LPC is pulled down to the VSS1 in the IC.
Input the γ -corrected power supplies from outside by using operational
amplifier. During the gray scale voltage output, be sure to keep the gray
scale level power supply at a constant level. Make sure to maintain the
following relationships.
VDD2 – 0.2 V V0 > V1 > V2 > ... ..., > V6 > V7 0.5 VDD2 + 0.5 V
0.5 VDD2 – 0.5 V V8 > V9 > V10 > ... ..., > V14 > V15 0.5 VSS2 + 0.2 V
Normally, set the TEST pin to H level or leave open.
This pin is pulled up to VDD1 in the IC.
2.5 to 3.6 V
12.5 to 15.5 V
Grounding
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0-V15 in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.47 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter,
insertion of a bypass capacitor of about 0.1 µF is also advised between the γ-corrected
power supply terminals (V0, V1, V2,....., V15) and VSS2.
Data Sheet S15953EJ2V0DS
5


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