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PDF UPD160010 Data sheet ( Hoja de datos )
| Número de pieza | UPD160010 | |
| Descripción | 384-/360-OUTPUT TFT-LCD SOURCE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
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µPD160010
384-/360-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256 GRAY SCALES, mini-LVDS INTERFACE SUPPORTED)
DESCRIPTION
The µ PD160010 is a source driver for TFT-LCDS that supports the display of 256 gray scales and employs mini-LVDS
interface. Which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A
converter and 10-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 − 0.2
V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line
inversion, n-line inversion, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and
even output pins respectively output gray scale voltages of differing polarity. Because of the incorporation of mini-LVDS
interface, the data transfer speed has improved and the amount of wiring on the PCB has been significantly reduced.
Remark "mini-LVDS" is the technology with Texas Instruments applied LVDS technology and developed.
(LVDS: Low Voltage Differential Signaling)
FEATURES
• Differential interface: CLK, gray scale data,
• CMOS interface: STHR(L), R,/L, STB, SB, POL, Osel, Vsel1, Vsel2, SRC, ORC, RxBIAS1, RxBIAS2
• 384/360 outputs (Osel)
• Capable of outputting 256 values by means of 10-by-2 external power modules (20 units) and a D/A converter
• Logic power supply voltage (VDD1): 2.7 to 3.6V
• Driver power supply voltage (VDD2): 10.0 to 16.5V
• High-speed data transfer: fCLK = 190 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)
• Output dynamic range: VSS2 + 0.2 V to VDD2 − 0.2 V
• Apply for dot-line inversion, n-line inversion
• Output voltage polarity inversion function (POL)
★ ORDERING INFORMATION
Part Number
µPD160010N-xxx
µPD160010NL-xxx
Package
TCP (TAB package)
COF (COF package)
Remark The TCP/COF’s external shape is customized. To order the required shape, please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16316EJ2V0DS00 (2nd edition)
Date Published March 2004 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2003
1 page  
µPD160010
Pin Symbol
Vsel1, Vsel2
Pin Name
VDD2 selector
I/O
Input
(CMOS)
www.DataSheet4U.com
(2/2)
Description
This pin controls the bias current of output amplifier.
Logic input to Vsel1 and Vsel2 have a dependence on VDD2 and load condition and so
on. Output waveform simulation should be done before decision.
Vsel1
Vsel2
VDD2 Range (reference)
L L 10.5 V TYP.
L H 12.5 V TYP.
H L 16.0 V TYP.
H H Non-assign
V0 to V19
VDD1D
VDD1A
VDD2
VSS1D
VSS1A
VSS2
TEST
γ -corrected power
supplies
Low-voltage logic
power supply
Low-voltage analog
power supply
Driver power supply
Low-voltage logic
ground
Low-voltage analog
ground
Driver ground
TEST
−
−
−
−
−
−
−
Input
(CMOS)
Input the γ -corrected power supplies from outside. Make sure to maintain the
following relationships. During the gray scale voltage output, be sure to keep the
gray scale level power supply at a constant level.
VDD2 − 0.2 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 ≥ 0.5 VDD2
0.5 VDD2 ≥ V10 > V11 >V12 > V13 > V14 > V15 > V16 >V17 > V18 > V19 ≥ VSS2 + 0.2 V
2.7 to 3.6 V
VDD1D and VDD1A should be same electric potential.
2.7 to 3.6 V
VDD1D and VDD1A should be same electric potential.
10.0 to 16.5 V
Ground for internal logic circuit.
Please wire VSS1D and VSS1A in external circuit boards.
Ground for internal mini-LVDS receiver circuit.
Please wire VSS1D and VSS1A in external circuit boards.
Ground for internal high voltage circuit.
Please leave these pins open in normal operation mode.
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0-V19 in that order. Reverse this
sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.47 µ F bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter,
insertion of a bypass capacitor of about 0.01 µ F is also advised between the γ -corrected power
supply terminals (V0, V1, V2,....., V19) and VSS2.
Data Sheet S16316EJ2V0DS
5
5 Page 
6. FUNCTION DESCRIPTION
µPD160010
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6.1 Input Data Mapping
Display data and control data (RST) are input to D0(+/−) to D3(+/−).
Data mapping is changed in response to the mode, and the mode is changed by STB.
<Data Input Mode>
CL K (+)
D0(+)
D1(+)
D2(+)
D3(+)
D00 D01 D02 D03 D04 D05 D06 D07 D00 D01
D10 D11 D12 D13 D14 D15 D16 D17 D10 D11
D20 D21 D22 D23 D24 D25 D26 D27 D20 D21
D30 D31 D32 D33 D34 D35 D36 D37 D30 D31
Data Input Cycle
6.2 Composition of Display Data
MSB
LSB
Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0
Remark n = 0 to 3
Data Sheet S16316EJ2V0DS
11
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet UPD160010.PDF ] | |
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