GS815018AB-300 Datasheet PDF - GSI Technology
Part Number | GS815018AB-300 | |
Description | 1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM | |
Manufacturers | GSI Technology | |
Logo | ||
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GS815018/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250
119-Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 36
18Mb Register-Register Late Write SRAM
250 MHz–357 MHz
2.5 V VDD
HSTL I/O
Features
• Register-Register Late Write mode, Pipelined Read mode
• 2.5 V +200/–200 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• ZQ controlled programmable output drivers
• Dual Cycle Deselect
• Fully coherent read and write pipelines
• Byte write operation (9-bit bytes)
• Differential HSTL clock inputs, K and K
• Asynchronous output enable
• Sleep mode via ZZ
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• JEDEC-standard 119-bump BGA package
• Pb-Free 119-bump BGA package available
Family Overview
GS815018/36A are 18,874,368-bit (18Mb) high performance
SRAMs. This family of wide, low voltage HSTL I/O SRAMs
is designed to operate at the speeds needed to implement
economical high performance cache systems.
Functional Description
Because GS815018/36A are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
GS815018/36A support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
GS815018/36A are implemented with high performance
technology and are packaged in a 119-bump BGA.
Mode Control
There are two mode control select pins (M1 and M2), which
allow the user to set the correct read protocol for the design.
The GS815018/36A support single clock Pipeline mode, which
directly affects the two mode control select pins. In order for
the part to fuction correctly, and as specified, M1 must be tied
to VSS and M2 must be tied to VDD or VDDQ. This must be set
at power-up and should not be changed during operation.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Pipeline
Parameter Synopsis
-357 -333 -300 -250 Unit
Cycle
tKHQV
2.8 3.0 3.3 4.0 ns
1.4 1.5 1.6 2.0 ns
Curr (x18)
Curr (x36)
600 550 500 450 mA
650 600 550 500 mA
Rev: 1.05 10/2005
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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GS815018/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250
Write Operations
Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge
of the K clock (and falling edge of the K clock).
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control
inputs are captured by the same clock edge used to capture SW.
Example of x36 Byte Write Truth Table
Function
Read
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write all Bytes
Write Abort
SW Ba Bb Bc Bd
HX X X X
LL H H H
LH L H H
LH H L H
LH H H L
LL L L L
LH H H H
Rev: 1.05 10/2005
5/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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Information | Total 25 Pages | |
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GS815018AB-300 | The function is 1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM. GSI Technology | |
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