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PDF HYB18L512160BF-7.5 Data sheet ( Hoja de datos )
| Número de pieza | HYB18L512160BF-7.5 | |
| Descripción | DRAMs for Mobile Applications 512-Mbit Mobile-RAM | |
| Fabricantes | Qimonda AG | |
| Logotipo |  |
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HYB18L512160BF-7.5
HYE18L512160BF-7.5
DRAMs for Mobile Applications
512-Mbit Mobile-RAM
RoHS compliant
December 2006
www.DataSheet4U.com
Data Sheet
Rev. 1.22
1 page  
1.2 Pin Configuration
Data Sheet.
www.DataSheet4U.com
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
FIGURE 1
Standard Ballout 512-Mbit Mobile-RAM
6 33 $1 63 31 ! 6 $$ 1 $1 6 $$
$1 $1 6 $$ 1 " 6 33 1 $1 $ 1
$1 $1 63 31 # 6 $$ 1 $1 $ 1
$1 $1 6 $$ 1 $ 6 33 1 $1 $ 1
$1 .# 6 33 % 6 $$ ,$ 1 - $ 1
5$ 1 - #, + #+ % & # !3 2! 3 7%
! ! ! ' "! "! # 3
! ! ! ( ! ! ! ! 0
6 33 ! ! * ! ! 6 $$
1.3 Description
The HY[B/E]18L512160BF is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The HY[B/E]18L512160BF achieves high speed data transfer rates by employing a chip architecture that prefetches multiple
bits and then synchronizes the output data to the system clock. Read and write accesses are burst-oriented. Accesses start at
a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence.
The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.
The HY[B/E]18L512160BF is specially designed for mobile applications. It operates from a 1.8 V power supply. Power
consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced
by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power Down (PD) mode is available as well as a non-data-retaining Deep Power Down (DPD)
mode.
The HY[B/E]18L512160BF is housed in a Dual-Die 54-ball PG-TFBGA package. It is available in Commercial (0 °C to +70 °C)
and Extended (-25 °C to +85 °C) temperature ranges.
Rev. 1.22, 2006-12
01132005-06IU-IGVM
5
5 Page 
Data Sheet.
www.DataSheet4U.com
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
Burst Length
8
Full Page
Starting Column Address
A2 A1 A0
000
001
010
011
100
101
110
111
nnn
Order of Accesses Within a Burst
Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2, …
Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
not supported
Notes
1. For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block.
2. For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block.
3. For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block.
4. For a full page burst, A0-Ai select the starting data element.
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block.
2.2.1.2 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved. This is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by:
• the burst length
• the burst type
• the starting column address
This is listed in Table 6.
2.2.1.3 Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the
availability of the first segment of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock edge n + m
(for more detailed information, please refer to the READ command description).
2.2.1.4 Write Burst Mode
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write accesses
consist of single data elements only.
Rev. 1.22, 2006-12
01132005-06IU-IGVM
11
11 Page | ||
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