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PDF ICS180-02 Data sheet ( Hoja de datos )

Número de pieza ICS180-02
Descripción Low EMI Clock Generator
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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ICS180-02
Low EMI Clowcwkw.DGateaSnheeetr4aU.tcoomr
Description
The ICS180-02 generates a low EMI output clock from
a clock or crystal input. The device uses ICS’
proprietary mix of analog and digital Phase-Locked
Loop (PLL) technology to spread the frequency
spectrum of the output, thereby reducing the frequency
amplitude peaks by several dB.
The ICS180-02 offers down spread selection of -1.25%
and -3.75%. Refer to the MK1714-01/02 for the widest
selection of input frequencies and multipliers.
ICS offers a complete line of EMI reducing clock
generators. Consult us when you need to remove
crystals and oscillators from your board.
Features
Pin and function compatible to Cypress W180-02
Packaged in 8-pin SOIC
Provides a spread spectrum output clock
Accepts a clock input and provides same frequency
dithered output
Input frequency of 8 to 15 MHz
Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
Spread percentage selection for -1.25% and -3.75%
Operating voltage of 3.3 V and 5 V
Advanced, low-power CMOS process
Block Diagram
VDD
FS1
SSON#
SS%
X1/CLKIN
X2
Clock Buffer/
C ry sta l
O sc illa to r
PLL Clock
S y n th e s is
and Spread
Spectrum
C ircu itry
CLK
GND
MDS 180-02 A
1
Revision 110404
Integrated Circuit Systemsl525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com

1 page




ICS180-02 pdf
ICS180-02
LOW EMI CLOCK GENERATOR
www.DataSheet4U.com
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V±5% or 5 V±10%, Ambient Temperature 0 to +70° C, CL=15 pf
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input/Output Frequency
15 28 MHz
Input Clock Duty Cycle
Time above VDD/2
40
60 %
Output Clock Duty Cycle
Note 1
40 50 60 %
Output Rise Time
Output Fall Time
Jitter
tOR 0.8 to 2.4 V, note 1
tOF 2.4 to 0.8 V, note 1
Cycle-to-cycle
2 5 ns
2 5 ns
250 300 ps
Note 1: Measured with 15 pF load
Thermal Characteristics
Parameter
Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
150
140
θJA 3 m/s air flow
120
Thermal Resistance Junction to Case θJC
40
Marking Diagram
85
Notes:
1. ###### is the lot number.
°C/W
°C/W
°C/W
°C/W
180M-02
######
YYWW
2. YYWW is the last two digits of the year and week
that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. Bottom marking: country of origin.
14
Marking Diagram (Pb free)
85
180M02LF
######
YYWW
14
MDS 180-02 A
5
Revision 110404
Integrated Circuit Systemsl 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201l www.icst.com

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