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PDF 74LVC3G06 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC3G06 | |
| Descripción | Triple inverter | |
| Fabricantes | NXP Semiconductors | |
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74LVC3G06
Triple inverter with open-drain output
Rev. 03 — 01 February 2005
www.DataSheet4U.com
Product data sheet
1. General description
The 74LVC3G06 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC3G06 provides three inverting buffers.
The output of this device is an open drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant input/output for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V).
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s −24 mA output drive (VCC = 3.0 V)
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C.
1 page  
Philips Semiconductors
74LVC3G06www.DataSheet4U.com
Triple inverter with open-drain output
10. Recommended operating conditions
Table 7:
Symbol
VCC
VI
VO
Tamb
tr, tf
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
active mode
ambient
temperature
Power-down mode; VCC = 0 V
input rise and fall VCC = 1.65 V to 2.7 V
times
VCC = 2.7 V to 5.5 V
Min Typ
1.65 -
0-
0-
0-
−40 -
Max Unit
5.5 V
5.5 V
VCC V
5.5 V
+125 °C
0-
0-
20 ns/V
10 ns/V
11. Static characteristics
Table 8: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
Tamb = −40 °C to +85 °C [1]
VIH
HIGH-level input
VCC = 1.65 V to 1.95 V
voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
LOW-level input
VCC = 1.65 V to 1.95 V
voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VOL
LOW-level output
VI = VIH or VIL
voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
ILI input leakage current VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V
IOZ
3-state output
VI = VIH or VIL; VO = VCC or GND;
OFF-state current VCC = 5.5 V
Ioff power-off leakage VI or VO = 5.5 V; VCC = 0 V
current
0.65 × VCC -
1.7 -
2.0 -
0.7 × VCC -
--
--
--
--
--
--
--
--
--
--
[2] -
±0.1
- ±0.1
- ±0.1
ICC
∆ICC
quiescent supply
current
additional quiescent
supply current per
pin
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
[2] -
0.1
5
Max Unit
-V
-V
-V
-V
0.35 × VCC V
0.7 V
0.8 V
0.3 × VCC V
0.1 V
0.45 V
0.3 V
0.4 V
0.55 V
0.55 V
±5 µA
±10 µA
±10 µA
10 µA
500 µA
9397 750 14541
Product data sheet
Rev. 03 — 01 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 15
5 Page 
Philips Semiconductors
74LVC3G06www.DataSheet4U.com
Triple inverter with open-drain output
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
y
Z
8
5
pin 1 index
E
c
HE
A A2
A1
1
e
4
bp w M
detail X
A
X
vM A
Q
(A3)
θ
Lp
L
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1) E(2)
e
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
HE
3.2
3.0
OUTLINE
VERSION
SOT765-1
IEC
REFERENCES
JEDEC
JEITA
MO-187
L Lp Q v w y Z(1) θ
0.4
0.40 0.21
0.15 0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
Fig 9. Package outline SOT765-1 (VSSOP8).
9397 750 14541
Product data sheet
Rev. 03 — 01 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 15
11 Page | ||
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| PDF Descargar | [ Datasheet 74LVC3G06.PDF ] | |
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