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PDF 74LVC1G74 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC1G74 | |
| Descripción | Single D-type flip-flop | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVC1G74
www.DataSheet4U.com
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 05 — 9 August 2007
Product data sheet
1. General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant inputs for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V)
s ±24 mA output drive (VCC = 3.0 V)
s ESD protection:
x HBM EIA/JESD22-A114E exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page  
NXP Semiconductors
74LVC1G74www.DataSheet4U.com
Single D-type flip-flop with set and reset; positive edge trigger
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
VCC supply voltage
IIK
input clamping current
VI < 0 V
VI input voltage
IOK
output clamping current
VO > VCC or VO < 0 V
VO output voltage
Active mode
Power-down mode
−0.5
−50
[1] −0.5
-
[1][2] −0.5
[1][2] −0.5
+6.5
-
+6.5
±50
VCC + 0.5
+6.5
V
mA
V
mA
V
V
IO output current
VO = 0 V to VCC
- ±50 mA
ICC
IGND
Ptot
Tstg
supply current
ground current
total power dissipation
storage temperature
Tamb = −40 °C to +125 °C
-
−100
[3] -
−65
100
-
300
+150
mA
mA
mW
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
VI
VO
Tamb
∆t/∆V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
Active mode
ambient temperature
Power-down mode; VCC = 0 V
input transition rise and fall
rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
Min Typ Max Unit
1.65 -
5.5 V
0 - 5.5 V
0
-
VCC
V
0 - 5.5 V
−40 -
+125 °C
- - 20 ns/V
- - 10 ns/V
74LVC1G74_5
Product data sheet
Rev. 05 — 9 August 2007
© NXP B.V. 2007. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
74LVC1G74www.DataSheet4U.com
Single D-type flip-flop with set and reset; positive edge trigger
VI
CP input
GND
VI
SD input
GND
VI
RD input
GND
VOH
Q output
VOL
VOH
Q output
VOL
VM
tW
t PLH
VM
VM
t PHL
VM
t rec
tW
VM
t PHL
t rec
t PLH
mnb142
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and
the RD to CP removal time
74LVC1G74_5
Product data sheet
Rev. 05 — 9 August 2007
© NXP B.V. 2007. All rights reserved.
11 of 19
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| PDF Descargar | [ Datasheet 74LVC1G74.PDF ] | |
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