|
|
PDF LC72147V Data sheet ( Hoja de datos )
| Número de pieza | LC72147V | |
| Descripción | PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LC72147V (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
Ordering number : ENN6675
CMOS IC
LC72147V
PLL Frequency Synthesizer for Electronic Tuning
in Car Audio Systems
Overview
The LC72147V is a PLL frequency synthesizer for car
audio systems. It can implement high-performance
multifunction tuners and features a crystal oscillator
circuit that supports AM up-conversion, a fast locking
circuit, an A/D converter, and an LA1783/1750 IF counter
buffer control pin.
Functions
• High-speed programmable divider
— FMIN: 10 to 180 MHz: Pulse swallower type
• IF counter
— HCTR: 0.4 to 25 MHz: Frequency measurement
• Crystal oscillator: One of the following 4 frequencies
may be selected: 10.35, 10.25, 7.2, and 4.5 MHz
Reference frequency
— One of 12 frequencies may be selected (when a 7.2
or 4.5 MHz crystal is used)
100*1, 50, 30*2, 25, 12.5, 6.25, 3.125, 10, 9*2, 5, 3*2,
1 kHz
Notes: 1. Cannot be used when a 10.35 or 10.25 MHz
crystal is used
2. Cannot be used when a 10.25 MHz crystal
is used
• Phase comparator
— Supports dead band control
— Built-in unlock detection circuit
— Sub-charge pump for fast locking
— Built-in deadlock clearing circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports — General-purpose I/O: 5 pins
— Output: n-channel: 3 pins, CMOS: 2 pins
— IFBC pin (LA1783/1750 IF counter buffer control
pin)
• Serial data I/O
— Supports communication with the controller in the
CCB format.
• Operating ranges
— Supply voltage (VDD): 4.5 to 6.5 V
— Built-in regulator voltage (Vreg): 3.0 V (±10%)
— Operating temperature: –40 to +85°C
• Package
— SSOP-24
Package Dimensions
unit: mm
3175A-SSOP24
[LC72147V]
24 13
1 12 0.15
8.0
0.22 0.65 0.43 SANYO: SSOP24
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1300RM (OT) No. 6675-1/22
1 page  
Pin Functions
Pin No. Symbol
1 XIN
24 XOUT
Usage
X’tal OSC
LC72147V
Function
• Crystal oscillator connection.
(4.5, 7.2, 10.25, or 10.35 MHz)
• FMIN is selected by setting DVS in the control data to 1.
• Input frequency: 10 to 180 MHz
12
FMIN
Local oscillator signal input
• The signal is transmitted to the swallow counter.
• The divisor can be set to a value in the range 272 to 65,535.
23 CE
21 CL
22 DI
Chip enable
Clock
Input data
• This pin must be set to the high level when inputting serial data to the
LC72147V DI pin and when outputting serial data from the DO pin.
• Data synchronization clock signal used when inputting serial data to
the LC72147V DI pin and when outputting serial data from the DO pin.
• Serial data input for transferring data from the controller to the
LC72147V.
20 DO
Output data
• Serial data output for transferring data from the LC72147V to the
controller.
4 VDD
5 Vreg
6 VSS
Power
Regulator output
Ground
• LC72147V power supply. A voltage in the range 4.5 to 6.5 V must be
provided when the PLL circuit is operating.
• The power-on reset circuit operates when power is first applied.
• Regulator output. A capacitor must be inserted between Vreg and
VSS.
• The output voltage (3.0 V ±10%) is supplied to internal circuits.
• LC72147V ground.
Pin circuit
S
S
S
———
———
———
14 IFBC
IF buffer control
• The LC72147V can control the LA1783/1750 IF buffer output.
• This is a 3-state output. (0 V, Vreg/2 = 1.5 V, and Vreg = 3 V)
• General-purpose I/O ports.
16 I/O-1
• The outputs are open-drain circuits.
17 I/O-2 General-purpose I/O ports • After the power-on reset, I/O-1 and I/O-2 function as input ports. I/O-
3 functions as an output port fixed at the low level.
2 I/O-3
• The input/output state of these ports can be set using the I/O-1 to
I/O-3 bits in the serial data sent from the controller.
Continued on next page.
No. 6675-5/22
5 Page 
Continued from preceding page.
No. Control block/data
General-purpose counter
control data
CTS, CTE
(6)
GT0, GT1
CTP
CTC
I/O port control data
(7)
IO-1 to I/O-5
Output port data
(8)
OUT1 to OUT5
IFBC port control data
(9)
IFB0, IFB1
LC72147V
Content
• Selects the general-purpose counter input pin (HCTR).
CTS = 1: Selects the HSTR pin.
CTS = 0: Pulls down the HCTR pin.
• General-purpose counter measurement start data
CTE = 1: Starts the counter.
CTE = 0: Resets the counter.
• Determines the measurement time (frequency mode) and number of periods (period
mode).
Related data
GT1
0
0
1
1
GT0
0
1
0
1
Frequency measurement
Wait time
Measurement time
CTP = 0 CTP = 1
4 ms
3 to 4 ms 1 to 2 ms
8 3 to 4 ms 1 to 2 ms
32 7 to 8 ms 1 to 2 ms
64 7 to 8 ms 1 to 2 ms
Period measurement
mode
One period
One period
Two periods
Two periods
• CTP = 0: When the counter has been reset (CTE = 0), pulls down the general-purpose
counter input.
CTP = 1: When the counter has been reset (CTE = 0), does not pull down the general-
purpose counter input, and shortens the wait time.
However, immediately after CTP is set to 1, the counter start must be delayed
until the general-purpose counter input pin has been biased.
• The input sensitivity is reduced when CTC is set to 1. (Sensitivity: 10 to 30 mV rms)
• Data that specifies the I/O direction of the I/O ports.
[Data] = 0: Input port
1: Output port
*: After the power-on reset, the I/O-1, I/O-2, I/O-4, and I/O-5 are set up as input ports. I/O-3
is set up as an output port.
OUT1 to OUT5
ULD
• Data that determines the output from output ports O-1 to O-5.
[Data] = 1: Open or high level.
0: Low
*: Invalid when the corresponding port is set up as an input port or as the unlock state
indicator output.
I/O-1 to I/O-5
ULD
• Determines the 3-value output of the IFBC port.
IFB0 IFB1
00
01
10
11
IFBC output
Mid (Vreg/2 = 1.5 V)
Low (0 V)
Mid (Vreg/2 = 1.5 V)
High (Vreg = 3.0 V)
*: When PLL inhibit and crystal oscillator stop mode (R0 = 0, R1 = R2 = R3 = 1), the IFBC
output is set to the open state. This output goes to the mid level after the power-on reset.
Continued on next page.
No. 6675-11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LC72147V.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LC72147V | PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems | Sanyo Semicon Device |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |