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PDF ADP130 Data sheet ( Hoja de datos )
| Número de pieza | ADP130 | |
| Descripción | CMOS Linear Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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350 mA, Low VIN, Low Quiescent Current,www.DataSheet4U.com
CMOS Linear Regulator
ADP130
FEATURES
350 mA maximum output current
Input voltage supply range
VBIAS = 2.3 V to 5.5 V
VIN = 1.2 V to 3.6 V
2.3 V < VIN < 3.6 V, VIN can be tied to VBIAS
Very low dropout voltage: 17 mV @ 100 mA load
Low quiescent current: 25 μA @ no load
Low shutdown current: <1 μA
±1% accuracy @ 25°C
Excellent PSRR performance: 70 dB @ 10 kHz
Excellent load/line transient response
Optimized for small 1 μF ceramic capacitors
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
GENERAL DESCRIPTION
The ADP130 is a low quiescent current, low dropout linear regu-
lator. It is designed to operate in dual-supply mode with an input
voltage as low as 1.2 V to increase efficiency and provide up to
350 mA of output current. The low 17 mV dropout voltage at
a 100 mA load improves efficiency and allows operation over
a wider input voltage range.
A dual-supply power solution typically improves conversion
efficiency over a single-supply solution because the higher VBIAS
supply powers the part, and the lower VIN supply delivers current
to the load. The power dissipated in the device is thereby reduced.
The ADP130 is optimized for stable operation with small 1 μF
ceramic output capacitors. The ADP130 delivers good transient
performance with minimal board area.
TYPICAL APPLICATION CIRCUITS
VIN = 1.8V
1µF +
1 VIN
VOUT = 1.2V
VOUT 5
ADP130
1µF +
2 GND
3 EN
VBIAS
VBIAS = 3.6V
4
1µF +
Figure 1.
VIN = 2.8V
1µF +
1 VIN
VOUT = 1.8V
VOUT 5
ADP130
1µF +
2 GND
3 EN
VBIAS 4
VBIAS = 5V
+
1µF
Figure 2.
The ADP130 is available in the following 31 fixed output voltage
options:
• 0.80 V to 2.00 V in 50 mV steps
• 1.875 V, 2.25 V, 2.50 V, 2.775 V, 2.80 V, and 3.0 V
The ADP130 has a typical internal soft start time of 200 μs. Short-
circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP130 is available
in a tiny 5-lead TSOT package for the smallest footprint solution to
meet a variety of portable power applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VBIAS to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V to +3.6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +125°C
125°C
300°C
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in combi-
nation. The ADP130 may be damaged when junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low PCB thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The junction tempera-
ture (TJ) of the device is dependent on the ambient temperature
(TA), the power dissipation of the device (PD), and the junction-to-
ambient thermal resistance of the package (θJA). TJ is calculated
using the following formula:
TJ = TA + (PD × θJA)
ADP130www.DataSheet4U.com
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θJA are based on a four-layer, 4 in × 3 in circuit board.
For details about board construction, refer to JEDEC JESD51-7.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a four-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θJB). Therefore, ΨJB thermal paths
include convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD), using
the following formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
5-Lead TSOT
170
ΨJB
43
Unit
°C/W
ESD CAUTION
Rev. 0 | Page 5 of 20
5 Page 
90
1.8V
80
2.5V
3.0V
70
60
50
40
30
20
0.8V
1.2V
1.5V
10
0
0.01 0.1 1 10 100 1000
ILOAD (mA)
Figure 28. Output Noise vs. Load Current and Output Voltage
ILOAD
1mA TO 350mA LOAD STEP
2.5A/µs
1 200mA/DIV
2
VOUT
50mV/DIV
CH1 200mA
CH2 50mV
M40µs
T 10.40%
A CH1 92mA
Figure 29. Load Transient Response
VIN = 3.6V
VBIAS
3V TO 3.5V INPUT VOLTAGE STEP
1 2V/µs
500mV/DIV
VOUT
2mV/DIV
2
1
CH1 500mV
CH2 2mV
M40µs
T 10.20%
A CH1 3.35V
Figure 30. VBIAS Line Transient Response, VIN = 3.6 V, IOUT = 350 mA
ADP130www.DataSheet4U.com
VIN
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
2
VOUT
5mV/DIV
1
CH1 500mV
CH2 5mV
M20µs
T 10.20%
A CH1 3.37V
Figure 31. VIN Line Transient Response, VBIAS = 5 V, IOUT = 1 mA
VIN
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
2
VOUT
5mV/DIV
1
CH1 500mV
CH2 5mV
M20µs
T 10.20%
A CH1 3.27V
Figure 32. VIN Line Transient Response, VBIAS = 5 V, IOUT = 350 mA
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADP130.PDF ] | |
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