PDF ADP3211 Data sheet ( Hoja de datos )

Número de pieza	ADP3211
Descripción	Synchronous Buck Controller
Fabricantes	ON Semiconductor
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No Preview Available ! ADP3211, ADP3211A 7-Bit, Programmable, Single-Phase, Synchronous Buck Controller The ADP3211 is a highly efficient, single−phase, synchronous buck switching regulator controller. With its integrated driver, the ADP3211 is optimized for converting the notebook battery voltage to the supply voltage required by high performance Intel chipsets. An internal 7−bit DAC is used to read a VID code directly from the chip−set or the CPU and to set the GMCH render voltage or the CPU core voltage to a value within the range of 0 V to 1.5 V. The ADP3211 uses a multi−mode architecture. It provides programmable switching frequency that can be optimized for efficiency depending on the output current requirement. In addition, the ADP3211 includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The ADP3211 also provides accurate and reliable current overload protection and a delayed power−good output. The IC supports on−the−fly (OTF) output voltage changes requested by the chip−set. The ADP3211 has a boot voltage of 1.1 V for IMVP−6.5 applications in CPU mode. The ADP3211A has a boot voltage of 1.2 V in CPU mode. The ADP3211 is specified over the extended commercial temperature range of −10°C to 100°C and is available in a 32−lead QFN. Features • Single−Chip Solution ♦ Fully Compatible with the Intel® IMVP−6.5t CPU and GMCH Chipset Voltage Regulator Specifications Integrated MOSFET Drivers • Input Voltage Range of 3.3 V to 22 V www.Dat•aS±he7emt4UV.cWomorst−Case Differentially Sensed Core Voltage Error Overtemperature • Automatic Power−Saving Modes Maximize Efficiency During Light Load Operation • Soft Transient Control Reduces Inrush Current and Audio Noise • Independent Current Limit and Load Line Setting Inputs for Additional Design Flexibility • Built−in Power−Good Masking Supports Voltage Identification (VID) OTF Transients • 7−Bit, Digitally Programmable DAC with 0 V to 1.5 V Output • Short−Circuit Protection • Current Monitor Output Signal • This is a Pb−Free Device • Fully RoHS Compliant • 32−Lead QFN Applications • Notebook Power Supplies for Next Generation Intel Chipsets • Intel Netbook Atom Processors http://onsemi.com 1 32 QFN32 MN SUFFIX CASE 488AM MARKING DIAGRAM 1 xxxxxx xxxxxx AWLYYWW xxx = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week PIN ASSIGNMENT PWRGD IMON CLKEN FBRTN FB COMP GPU ILIM 1 ADP3211 ADP3211A (top view) VCC BST DRVH SW PVCC DRVL PGND GND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 31 of this data sheet. © Semiconductor Components Industries, LLC, 2009 April, 2009 − Rev. 0 1 Publication Order Number: ADP3211/D 1 page ADP3211, ADP3211A ELECTRICAL CHARACTERISTICS (VCC = PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, VVID = VDAC = 1.2 V, TA = −10°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign. Parameter Symbol Conditions Min Typ Max Units VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP) FB, LLINE Voltage Range (Note 2) VFB, VLLINE Relative to CSREF = VDAC −200 +200 mV FB, LLINE Offset Voltage (Note 2) VOSVEA Relative to CSREF = VDAC −0.5 +0.5 mV FB Bias Current LLINE Bias Current LLINE Positioning Accuracy COMP Voltage Range COMP Current COMP Slew Rate IFB ILL VFB − VDAC VCOMP ICOMP SRCOMP Gain Bandwidth (Note 2) GBW VID DAC VOLTAGE REFERENCE VDAC Voltage Range (Note 2) VDAC Accuracy VFB − VDAC VDAC Differential Non−linearity (Note 2) VDAC Line Regulation ΔVFB VDAC Boot Voltage VBOOTFB Soft−Start Delay (Note 2) www.DataSShoefte−tS4Uta.rctoTmime Boot Delay VDAC Slew Rate tDSS tSS tBOOT Measured on FB relative to nominal VDAC LLINE forced 80 mV below CSREF Voltage range of interest COMP = 2.0 V, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF CCOMP = 10 pF, CSREF = VDAC, Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF Non−inverting unit gain configuration, RFB = 1 kW See VID Code Table Measured on FB (includes offset), relative to nominal VDAC VDAC = 0.3000 V to 1.2000 V VDAC = 1.2125 V to 1.5000 V VCC = 4.75 V to 5.25 V Measured during boot delay period, GPU = 0 V ADP3211 ADP3211A Measured from EN pos edge to FB = 50 mV Measured from EN pos edge to FB settles to Vboot = 1.1 V within −5% Measured from FB settling to Vboot = 1.1 V within −5% to CLKEN neg edge Soft−Start Arbitrary VID step −1.0 −50 −78 0.85 +1.0 +50 −80 −82 4.0 −650 2.0 10 −10 20 mA nA mV V mA mA V/ms MHz 0 1.5 −7.0 −9.0 +7.0 +9.0 −1.0 +1.0 0.05 1.100 1.200 200 1.4 V mV LSB % V ms ms 100 ms 0.0625 1.0 LSB/ms FBRTN Current IFBRTN VOLTAGE MONITORING and PROTECTION − Power Good CSREF Undervoltage Threshold CSREF Overvoltage Threshold CSREF Crowbar Voltage Threshold VUVCSREF − VDAC VOVCSREF − VDAC VCBCSREF Relative to nominal VDAC Voltage Relative to nominal VDAC Voltage Relative to FBRTN CSREF Reverse Voltage Threshold VRVCSREF Relative to FBRTN, Latchoff Mode CSREF is falling CSREF is rising 70 200 mA −360 −300 −240 150 200 250 1.5 1.55 1.6 −350 −300 −75 −5.0 mV mV V mV PWRGD Low Voltage VPWRGD IPWRGD(SINK) = 4 mA 75 200 mV 1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 5 5 Page ADP3211, ADP3211A TYPICAL PERFORMANCE CHARACTERISTICS Output Voltage 1 Switch Node 2 1: 50mV/div 2: 10V/div 40 ms/div Input = 12V Output = 1.2V 15A to 3A Step Figure 15. Load Transient Output Voltage 1 Switch Node 2 1: 100mV/div 2: 10V/div 200 ms/div Input = 12V No Load DVID = 250mV Figure 16. VID on the Fly Output Voltage 1 Switch Node 2 1: 100mV/div 2: 10V/div 200 ms/div Input = 12V 10A Load DVID = 250mV www.DataSheet4U.com Figure 17. VID on the Fly Output Voltage 1 2 3 CLKEN 4 1 : 500mV/div 2 : 10V/div Switch Node PWRGD 3 : 5V/div 4 : 2V/div 2ms/div Figure 18. Over Current Protection http://onsemi.com 11 11 Page

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