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PDF UPD161660 Data sheet ( Hoja de datos )
| Número de pieza | UPD161660 | |
| Descripción | POWER SUPPLY | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD161660
POWER SUPPLY FOR TFT-LCD DRIVER
DESCRIPTION
The µPD161660 is a power supply IC for TFT-LCD driver. This ICs can generate the levels which TFT-LCD driver
need, from 2.7 V.
FEATURES
• To generate 3 levels from single voltage input
• To integrate regulator circuit for source and gate driver
ORDERING INFORMATION
Part number
5 µPD161660P
Package
Chip
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representative.
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The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14799EJ1V0DS00 (1st edition)
Date Published May 2002 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
2000, 2002
1 page  
µPD161660
3. PIN FUNCTIONS
Symbol
VDC
VCC1
VSS
DVSS
VDD1
Pin Name
Power supply
Power supply
Ground
Ground
DC/DC converter output
Pad No.
7
42
40
49
15
VDD2
DC/DC converter output
16
VO
Rectangle signal output for
19
negative boost
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VT
VS
VREF
Regulator output
Regulator output
Reference voltage
input/output
DCON
DC/DC converter control
RGONP Regulator control
EXRVT
EXRVS
VT regulating resistor
selection
VS regulating resistor
selection
13
10
12
64
65
63
62
(1/2)
I/O Description
– Power supply for DC/DC converter.
– Power supply for logic circuit.
– Ground.
– Ground (for control pin pull-down)
– Boost voltage of DC/DC converter (x4, x5, x6 or x7).
The capacitors required for each boost level are shown
below.
• x4 boost: C1, C2, C6 (C3, C4, and C5 are not required)
• x5 boost: C1, C2, C3, C6 (C4, and C5 are not required)
• x6 boost: C1, C2, C3, C4, C6 (C5 is not required)
• x7 boost: C1, C2, C3, C4, C5, C6
– Boost voltage of DC/DC converter (x2 or x3). The boost
steps for VDD2 is selected by VCD2 pin. The capacitors
required for each boost level are shown below.
• x2 boost: C1
• x3 boost: C1, C2,
– Rectangle signal output for negative boost. The VO voltage
range is selected by VCE pin. The capacitors required for
each boost level are shown below.
<VCE = L>
• x3 boost: C1, C2
• x4 boost: C1, C2, C3
• x5 boost: C1, C2, C3, C4
• x6 boost: C1, C2, C3, C4, C5
<VCE = H>
• x4 boost: C1, C2, C6
• x5 boost: C1, C2, C3, C6
• x6 boost: C1, C2, C3, C4, C6
• x7 boost: C1, C2, C3, C4, C5, C6
– 15 V/12.5 V regulator output for gate driver.
– 5 V/4 V regulator output for source driver.
I/O The gate driver includes reference voltage for VB regulator.
When VREFSEL = H, external reference voltage can be
input. Reference voltage input/output pin of VT, VS
regulator.
I DC/DC converter ON/OFF control. Connect to DCON pin
of source driver.
I Regulator ON/OFF control. Connect to RGONP pin of
source driver.
I To select internal/external resistor for VT regulator.
I To select internal/external resistor for VS regulator.
Data Sheet S14799E1V0DS
5
5 Page 
µPD161660
that the gate output may be undefined and the DC/DC converter and the regulators may be on. If the B period is
sufficiently short however, it is unlikely that the display will be affected. Note that the gate output MAX value in the
B period must be determined separately as a specification of the LCD module.
The pins are re-fixed to the following levels by the source driver when the RESET command is input.
Note that the gate output is fixed to the VB level, and the DC/DC converter and the regulators are off.
DCON, RGONG, RGONP, OE1: L (low level)
OE2: H (high level)
~ Set a timing that ensures the DCON, RGONP, and RGONG pins are shifted to high level in that order after the
RESET command is input. At this time, the DC/DC converter and the regulators are on. Before that, the booster
level must have been set up (by BGRS, VCE, VCD2, PVCOM of R32 register and R34 register of the µPD161620) .
Note that the target timing of tDDRP and tRPRG (while the DC/DC converter output and regulator output is stable) is
tDDRP = approx. 50 ms and tRPRG = approx. 20 ms, but users are requested to set the final timing after sufficiently
evaluating the µPD161660 in the LCD module.
Input the DISPON command (↑part) after ensuring that all the power supplies are high level.
The source driver will start display with OE1 = H.
The target is tRGOE1 = approx. 1 ms, but users are requested to set the final timing after sufficiently evaluating the
µPD161660 in the LCD module.
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Data Sheet S14799E1V0DS
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet UPD161660.PDF ] | |
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