UPD4616112 Datasheet PDF - NEC
| Part Number | UPD4616112 | |
| Description | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT | |
| Manufacturers | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4616112
16M-BIT CMOS MOBILE SPECIFIED RAM
1M-WORD BY 16-BIT
Description
The µPD4616112 is a high speed, low power, 16,777,216 bits (1,048,576 words by 16 bits) CMOS mobile specified
RAM featuring low power static RAM compatible function and pin configuration.
The µPD4616112 is fabricated with advanced CMOS technology using one-transistor memory cell.
The µPD4616112 is packed in 48-pin TAPE FBGA.
Features
• 1,048,576 words by 16 bits organization
5 • Fast access time: 80, 90 ns (MAX.)
• Byte data control: /LB (I/O0 - I/O7), /UB (I/O8 - I/O15)
• Low voltage operation: VCC = 2.6 to 3.0 V
• Operating ambient temperature: TA = –20 to +70 °C
• Output Enable input for easy application
• Chip Enable input: /CS pin
• Standby Mode input: MODE pin
• Standby Mode1: Normal standby (Memory cell data hold valid)
• Standby Mode2: Memory cell data hold invalid
www.DataSheePtr4oUd.uccotmname
5 µPD4616112-BCxx
Access time Operating supply Operating ambient
ns (MAX.)
Voltage
temperature
°C
80, 90
2.6 to 3.0
–20 to +70
Supply current
At operating
mA (MAX.)
At standby
µA (MAX.)
35 100 / 10
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15085EJ5V0DS00 (5th edition)
Date Published October 2001 NS CP (K)
Printed in Japan
The mark 5 shows major revised points.
©
2000
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µPD4616112
Truth Table
/CS MODE /OE /WE /LB /UB
Mode
I/O Supply current
I/O0 - I/O7
I/O8 - I/O15
H H × × × × Not selected (Standby Mode 1) High impedance High impedance ISB1
H L × × × × Not selected (Standby Mode 2) High impedance High impedance ISB2
LHHH× ×
Output disable
High impedance High impedance
ICCA
LHL L
Word read
DOUT
DOUT
LH
Lower byte read
DOUT
High impedance
HL
Upper byte read
High impedance
DOUT
HH
Output disable
High impedance High impedance
×LLL
Word write
DIN DIN
LH
Lower byte write
DIN High impedance
HL
Upper byte write
High impedance
DIN
HH
Write abort
High impedance High impedance
Caution MODE pin must be fixed to High except Standby Mode 2.
Remark ×: VIH or VIL
5 Initialization
The µPD4616112 is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, before turning on the power, a 200 µs or longer wait time must precede any signal
toggling.
(2) After the wait time, read operation must be performed at least 3 times. After that, it can be normal operation.
Initialization Timing Chart
VCC (MIN.)
VCC
Address (Input)
www.DataSheet4U.com
MODE (Input)
VIH (MIN.)
/CS (Input) VIH (MIN.)
tRC tCP
Power On Wait Time
200µs
Read Operation 3 times
Normal
Operation
Cautions 1. Following power application, make MODE and /CS high level during the wait time interval.
2. Following power application, make MODE high level during the wait time and three read
operations.
3. The read operation must satisfy the specs described on page 10 (Read Cycle (BC Version)).
4. The address is don’t care (VIH or VIL) during read operation.
5. Read operation must be executed with toggled the /CS pin.
6. To prevent bus contention, it is recommended to set /OE to high level.
7. Do not input data to the I/O pins if /OE is low level during a read operation.
Data Sheet M15085EJ5V0DS
5
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| Information | Total 30 Pages | |
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| Download | [ UPD4616112.PDF Datasheet ] | |
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