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PDF 74AVCH4T245 Data sheet ( Hoja de datos )
| Número de pieza | 74AVCH4T245 | |
| Descripción | 4-bit dual supply translating transceiver | |
| Fabricantes | NXP Semiconductors | |
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74AVCH4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 01 — 6 August 2009
Product data sheet
1. General description
The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two data input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and
VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to
VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B outputs are in the high-impedance OFF-state. The bus hold
circuitry on the powered-up side always stays active.
The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
I Wide supply voltage range:
N VCC(A): 0.8 V to 3.6 V
N VCC(B): 0.8 V to 3.6 V
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3B exceeds 8000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Maximum data rates:
N 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
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1 page  
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
6. Functional description
Table 3. Function table[1]
Supply voltage
Input
VCC(A), VCC(B)
0.8 V to 3.6 V
nOE[2]
L
0.8 V to 3.6 V
L
0.8 V to 3.6 V
H
GND[3]
X
nDIR[2]
L
H
X
X
Input/output[3]
nAn[2]
nAn = nBn
input
Z
Z
nBn[2]
input
nBn = nAn
Z
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B).
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC(A)
VCC(B)
IIK
VI
IOK
VO
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
VI < 0 V
VO < 0 V
Active mode
Suspend or 3-state mode
−0.5
−0.5
−50
[1] −0.5
−50
[1][2][3] −0.5
[1] −0.5
+4.6
+4.6
-
+4.6
-
VCCO + 0.5
+4.6
V
V
mA
V
mA
V
V
IO output current
VO = 0 V to VCCO
[2] -
±50 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
ICC(A) or ICC(B)
Tamb = −40 °C to +125 °C
-
−100
−65
[4] -
100
-
+150
500
mA
mA
°C
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For SO16 package: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 package: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN16 package: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
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74AVCH4T245_1
Product data sheet
Rev. 01 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
5 of 26
5 Page 
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 9. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) = VCC(B)
0.8 V 1.2 V 1.5 V 1.8 V
CPD power dissipation A port: (direction nAn to 0.2 0.2 0.2 0.2
capacitance
nBn); output enabled
A port: (direction nAn to 0.2 0.2 0.2 0.2
nBn); output disabled
A port: (direction nBn to 9.5 9.7 9.8 9.9
nAn); output enabled
A port: (direction nBn to 0.6 0.6 0.6 0.6
nAn); output disabled
B port: (direction nAn to 9.5 9.7 9.8 9.9
nBn); output enabled
B port: (direction nAn to 0.6 0.6 0.6 0.6
nBn); output disabled
B port: (direction nBn to 0.2 0.2 0.2 0.2
nAn); output enabled
B port: (direction nBn to 0.2 0.2 0.2 0.2
nAn); output disabled
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
2.5 V
0.3
0.3
10.7
0.7
10.7
0.7
0.3
0.3
3.3 V
0.4
Unit
pF
0.4 pF
11.9 pF
0.7 pF
11.9 pF
0.7 pF
0.4 pF
0.4 pF
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74AVCH4T245_1
Product data sheet
Rev. 01 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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