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PDF ISL12059 Data sheet ( Hoja de datos )

Número de pieza ISL12059
Descripción Low Cost and Low Power I2C Bus Real Time Clock/Calendar
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL12059 Hoja de datos, Descripción, Manual

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ISL12059
® Low Cost and Low Power I2C BusReal Time Clock/Calendar
Data Sheet
June 15, 2009
FN6757.0
Low Power and Low Cost RTC
The ISL12059 device is a low power real time clock with
clock/calendar, and 512Hz/digital output function.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Pinout
ISL12059
(8 LD SOIC)
TOP VIEW
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Date, Month, and Year
• 512Hz Frequency Output
• I2C Bus
- 400kHz Data Transfer Rate
• Small Package Option
- 8 Ld SOIC Package
- Pb-Free (RoHS Compliant)
• Low Cost 3V Alternative to M41T00S, DS1340 and
ISL12008
X1 1
X2 2
NC 3
GND 4
8 VDD
7 FT/OUT
6 SCL
5 SDA
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• Point Of Sale Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
Ordering Information
.
PART
NUMBER
(Note)
PART
MARKING
VDD RANGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL12059IBZ
12059 IBZ
1.4 to 3.6
-40 to +85
8 Ld SOIC
M8.15
ISL12059IBZ-T*
12059 IBZ
1.4 to 3.6
-40 to +85
8 Ld SOIC (Tape and Reel) M8.15
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
I2C BusAll other trademarks mentioned are the property of their respective owners

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ISL12059 pdf
ISL12059
www.SDaDtaAShevest4US.cComL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
Symbol Table
WAVEFORM
INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A Center Line is
High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 3.0V
5.0V
SDA,
FT/OUT
1533Ω
FOR VOL= 0.4V
AND IOL = 3mA
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH VDD = 3.0V, VPULLUP = 5.0V
5 FN6757.0
June 15, 2009

5 Page





ISL12059 arduino
ISL12059
www.SDamtaSahleleOt4Uu.ctolimne Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45°
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1
0.0040 0.0098 0.10
0.25
-
B
0.013 0.020 0.33
0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.1890 0.1968 4.80
5.00
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC
1.27 BSC
-
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L
0.016 0.050 0.40
1.27
6
N8
87
α 0° 8° 0° 8° -
Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN6757.0
June 15, 2009

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