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PDF ST9040 Data sheet ( Hoja de datos )
| Número de pieza | ST9040 | |
| Descripción | 16K ROM HCMOS MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® ST9040
16K ROM HCMOS MCU
WITH EEPROM, RAM AND A/D CONVERTER
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time : 500ns
(12MHz internal)
Internal Memory :
ROM
16K bytes
RAM
256 bytes
EEPROM
512 bytes
224 general purpose registers available as RAM,
accumulators or index registers (register file)
80-pin PQFP package for ST9040Q
68-lead PLCC package for ST9040C
DMA controller, Interrupt handler and Serial Pe-
ripheral Interface as standard features
Up to 56 fully programmable I/O pins
Up to 8 external plus 1 non-maskableinterrupts
16 bit Timer with 8 bit Prescaler, able to be used
as a WatchdogTimer
Two 16 bit Multifunction Timers, each with an 8
bit prescaler and 13 operating modes
8 channel 8 bit Analog to Digital Converter, with
Analog Watchdogs and external references
Serial Communications Interface with asynchro-
nous and synchronous capability
Rich Instruction Set and 14 Addressingmodes
Division-by-Zero trap generation
Versatile developmenttools, including assembler,
linker, C-compiler, archiver, graphic oriented de-
buggerand hardware emulators
Real Time Operating System
Windowed and One Time Programmable EPROM
parts available for prototyping and pre-production
development phases
Pin to pin compatible with ST9036
PQFP80
PLCC68
(Ordering Information at the end of the Datasheet)
February 1997
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ST9040
1.1GENERAL DESCRIPTION
The ST9040 is a ROM member of the ST9 family of
microcontrollers, completely developed and pro-
duced by SGS-THOMSON Microelectronics using
a proprietary n-well HCMOS process.
The ST9040 peripheral and functional actions are
fully compatible throughout the ST903x/4x family.
This datasheet will thus provide only information
specific to this ROM device.
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST9036 ROM-BASED DE-
VICE FOR FURTHER DETAILS.
The nucleus of the ST9040 is the advanced Core
which includes the Central Processing Unit (CPU),
the Register File, a 16 bit Timer/Watchdog with 8
bit Prescaler, a Serial Peripheral Interface support-
ing S-bus, I2C-bus and IM-bus Interface,plus two 8
bit I/O ports. The Core has independent memory
and register buses allowing a high degree of pipe-
lining to add to the efficiency of the code execution
speed of the extensive instruction set. The power-
ful I/O capabilities demanded by microcontroller
applications are fulfilled by the ST9040 with up to
56 I/O lines dedicated to digital Input/Output.
These lines are grouped into up to seven 8 bit I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
an address/databus for interfacing external mem-
ory, timer inputs and outputs, analog inputs, exter-
nal interrupts and serial or parallel I/O with or
without handshake.
Three basic memory spaces are available to support
this wide range of configurations: Program Memory
(internaland external), Data Memory (internaland ex-
ternal)andtheRegisterFile, which includesthecontrol
andstatus registers of theon-chip peripherals.
Two 16 bit MultiFunction Timers, each with an 8 bit
Prescaler and 13 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functionsby the usage of the two associated
DMA channels for each timer. In addition there is
an 8 channel Analog to Digital Converter with inte-
gral sample and hold, fast 11µs conversion time
and 8 bit resolution. An Analog Watchdog feature
is included for two input channels.
Completing the device is a full duplex Serial Com-
munications Interface with an integral 110 to
375,000 baud rate generator, asynchronous and
1.5Mbyte/s synchronous capability (fully program-
mable format) and associated address/wake-up
option, plus two DMA channels.
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ST9040
EEPROM (Continued)
1.3.2.2 EEPROM Programming Procedure
The programming of a byte of EEPROMmemory is
equivalent to writing a byte into a RAM location af-
ter verifying that EEBUSY bit is low. Instructions
operating on word data (16 bits) will not access the
EEPROM.
The EEPROM ENABLE bit EEWEN must first be
set before writing to the EEPROM. When this bit is
low, attempts to write data to the EEPROM have
no affect, this prevents any spurious memory ac-
cesses from affecting the data in the EEPROM.
Termination of the write operation can be detected
by polling on the EEBUSY status bit, or by inter-
rupt, taking the interrupt vector from the External
Interrupt 4 channel. The selection of the interrupt is
made by EEPROM Interrupt enable bit EEIEN. It
should be noted that the Mask bit of External Inter-
rupt 4 should be set, and the Interrupt Pending bit
reset, before the setting of EEIEN to prevent un-
wanted interrupts. A delay (eg a nop instruction)
should also be included between the operationson
the mask and pending bits of External Interrupt 4.
If polling on EEBUSY is used, a delay of 6 INTCLK
clock cycles is necessary after the end of program-
ming, this can be a nop instruction or, normally,
therequired time to test the EEBUSY bit and to
branch to the next instruction will be sufficient.
While EEBUSY is active, any attempt to access the
EEPROM matrix will be aborted and the data read
will be invalid. EEBUSY is a read only bit and can-
not be reset by the user if active.
An erased bit of the EEPROM memory will read as
a logic “0”, while a programmed cell will be read as
a logic “1”. For applications requiring the highest
level of reliability, the Verify Mode, set by EEPROM
control register bit VRFY, allows the reading of the
EEPROM memory cells with a reduced gate volt-
age (typically 20%). If the EEPROM memory cell
has been correctly programmed, a logic “1” will be
read with the reduced voltage,otherwise a logic “0”
will be read.
1.3.2.3 Parallel Programming Procedure
Parallel programming is a feature of the EEPROM
macrocell. One up to sixteen bytes of a same row
can be programmed at once.
The constraint is that each of the bytes occur in the
same ROW of the EEPROM memory (A4 constant,
A3-A0 variable). To operate this mode, the Parallel
Mode enable bit, PLLEN, must be set. The data
written is then latched into buffers (at the ad-
dresses specified, which may be non-sequential)
and then transferred to the EEPROM memory by
the setting of the PLLST bit of the control register.
Both PLLST and PLLEN are internally reset at the
end of the programming cycle. Any attempt to read
the EEPROM memory when PLLEN is set will give
invalid data. In the event that the data in the buffer
latches is not required to be written into the memory
by the setting of PLLST, the correct way to terminate
the operation is to reset PLLEN and to perform a
dummy read of theEEPROMmemory. This termina-
tion will clear all data present in the latches.
1.3.2.4 EEPROM Programming Voltage
No external Vpp voltage is required, an internal
18Volt charge-pump gives the required energy by
a dedicated oscillator pumping at a typical fre-
quency of 5MHz, regardless of the external clock.
1.3.2.5 EEPROM Programming Time
No timing routine is required to control the pro-
gramming time as dedicated circuitry takes care of
the EEPROM programming time (The typical pro-
gramming time is 6ms).
1.3.2.6 EEPROM Interrupt Management
At the end of each write procedure the EEPROM
sends an interrupt request (if EEIEN bit is set). The
EEPROM shares its interrupt channel with the ex-
ternal interrupt source INT4, from which the priority
level is derived.
Care must be taken when EEIEN is reset. The as-
sociated external interrupt channel must be dis-
abled (by reseting bit 4 of EIMR, R244) along with
reseting the interrupt pending bit (bit 4 of EIPR,
R243) to prevent unwanted interrupts. A delay in-
struction (at least 1 nop instruction) must be in-
serted between these two operations
WARNING. The content of the EEPROM of the
ST9040 family after the out-going test at SGS-
THOMSON’s manufacturing location is not guar-
enteed.
11/56
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