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PDF CYRF69213 Data sheet ( Hoja de datos )
| Número de pieza | CYRF69213 | |
| Descripción | Programmable Radio on Chip Low Power | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRoC™ LP Features
• Single Device, Two Functions
— 8-bit, Flash based USB peripheral MCU function and
2.4 GHz radio transceiver function in a single device
• Flash-based Microcontroller Function
— M8C based 8-bit CPU, optimized for Human Interface
Devices (HID) applications
— 256 Bytes of SRAM
— 8 Kbytes of Flash memory with EEPROM emulation
— In-System reprogrammable through D+/D– pins.
— 16-bit free running timer
— Low power wake up timer
— 12-bit Programmable Interval Timer with interrupts
— Watchdog timer
• Industry-Leading 2.4 GHz Radio Transceiver Function
— Operates in the unlicensed worldwide Industrial,
Scientific and Medical (ISM) band
(2.4 GHz–2.483 GHz)
— DSSS data rates of up to 250 Kbps
— GFSK data rate of 1 Mbps
— –97 dBm receive sensitivity
— Programmable output power of up to +4 dBm
— Auto Transaction Sequencer (ATS)
— Framing CRC and Auto ACK
PRoC™ LP
CYRF69213
Block Diagram
Vbus
4.7uF
1-2 uF
CYRF69213
Programmable Radio on Chip
Low Power
— Received Signal Strength Indication (RSSI)
— Automatic Gain Control (AGC)
• Component Reduction
— Integrated 3.3V regulator
— Integrated pull up on D–
— GPIOs that require no external components
— Operates off a single crystal
• Flexible I/O
— High current drive on GPIO pins. Configurable 8-mA or
50-mA/pin current sink on designated pins
— Each GPIO pin supports high-impedance inputs, config-
urable pull up, open-drain output, CMOS/TTL inputs and
CMOS output
— Maskable intrrupts on all I/O pins
• USB Specification Compliance
— Conforms to USB Specification Version 2.0
— Conforms to USB HID Specification Version 1.1
— Supports one Low Speed USB device address
— Supports one control endpoint and two data end points
— Integrated USB Transceiver
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0 to 70°C
• Lead-free 40-lead QFN package
• Advanced development tools based on Cypress’s PSoC®
Tools
470nF
Microcontroller
P0_2:4,7
4
P1_6:7
2
Function
P1.5/MOSI
P1.4/SCK
P2_0:1
2
P1.3/nSS
D+/D-
2
RFbias
RFp
RFn
Radio
Function
IRQ/GPIO
MISO/GPIO
XOUT/GPIO
PACTL/GPIO
.....
12MHz
.......
470nF
Cypress Semiconductor Corporation
Document #: 001-07552 Rev. *B
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised February 20, 2007
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CYRF69213
Functional Block Overview
All the blocks that make up the PRoC LP are presented here.
2.4-GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
7 +4
60
5 –5
4 –10
3 –15
2 –20
1 –25
0 –30
Frequency Synthesizer
Before transmission or reception may commence, it is
necessary for the frequency synthesizer to settle. The settling
time varies depending on channel; 25 fast channels are
provided with a maximum settling time of 100 µs.
The ‘fast channels’ (<100-µs settling time) are every third
frequency, starting at 2400 MHz up to and including 2472 MHz
(for example, 0,3,6,9…….69 & 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, as well as EOP detection and length
field.
Data Rates and Data Transmission Modes
The SoC supports four different data transmission modes:
• In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
• In 8DR mode, 8 bits are encoded in each
DATA_CODE_ADR derived code symbol transmitted.
• In DDR mode, 2-bits are encoded in each
DATA_CODE_ADR derived code symbol transmitted. (As
in the CYWUSB6934 DDR mode).
• In SDR mode, 1 bit is encoded in each DATA_CODE_ADR
derived code symbol transmitted. (As in the CYWUSB6934
standard modes.)
Both 64-chip and 32-chip DATA_CODE_ADR codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduces
packet error rate in any given environment.
By combining the DATA_CODE_ADR code lengths and data
transmission modes described above, the CYRF69213 IC
supports the following data rates:
• 1000-kbps (GFSK)
• 250-kbps (32-chip 8DR)
• 125-kbps (64-chip 8DR)
• 62.5-kbps (32-chip DDR)
• 31.25-kbps (64-chip DDR)
• 15.625-kbps (64-chip SDR)
Lower data rates typically provide longer range and/or a more
robust link.
Link Layer Modes
The CYRF69213 IC device supports the following data packet
framing features:
SOP – Packets begin with a 2-symbol Start of Packet (SOP)
marker. This is required in GFSK and 8DR modes, but is
optional in DDR mode and is not supported in SDR mode; if
framing is disabled then an SOP event is inferred whenever
two successive correlations are detected. The
SOP_CODE_ADR code used for the SOP is different from that
used for the ‘body’ of the packet, and if desired may be a
different length. SOP must be configured to be the same
length on both sides of the link.
EOP – There are two options for detecting the end of a packet.
If SOP is enabled, then a packet length field may be enabled.
GFSK and 8DR must enable the length field. This is the first
8 bits after the SOP symbol, and is transmitted at the payload
data rate. If the length field is enabled, an End of Packet (EOP)
condition is inferred after reception of the number of bytes
defined in the length field, plus two bytes for the CRC16 (if
enabled—see below). The alternative to using the length field
is to infer an EOP condition from a configurable number of
successive non-correlations; this option is not available in
GFSK mode and is only recommended when using SDR
mode.
CRC16 – The device may be configured to append a 16-bit
CRC16 to each packet. The CRC16 uses the USB CRC
polynomial with the added programmability of the seed. If
enabled, the receiver will verify the calculated CRC16 for the
payload data against the received value in the CRC16 field.
The starting value for the CRC16 calculation is configurable,
and the CRC16 transmitted may be calculated using either the
loaded seed value or a zero seed; the received data CRC16
will be checked against both the configured and zero CRC16
seeds.
CRC16 detects the following errors:
• Any one bit in error
• Any two bits in error (no matter how far apart, which column,
and so on)
• Any odd number of bits in error (no matter where they are)
• An error burst as wide as the checksum itself
Figure 2 shows an example packet with SOP, CRC16 and
lengths fields enabled.
Document #: 001-07552 Rev. *B
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Table 6. CPU Stack Pointer Register (CPU_SP)
Bits 7:0
Stack Pointer [7:0]
8-bit data value holds a pointer to the current top-of-stack
CPU Program Counter High Register
Table 7. CPU Program Counter High Register (CPU_PCH)
Bit #
76543210
Field
Program Counter [15:8]
Read/Write
–
–
–
–
–
–
–
–
Default
00000
00
0
Bits 7:0
Program Counter [15:8]
8-bit data value holds the higher byte of the program counter
CPU Program Counter Low Register
Table 8. CPU Program Counter Low Register (CPU_PCL)
Bit #
76543210
Field
Program Counter [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
00000
00
0
Bits 7:0
Program Counter [7:0]
8-bit data value holds the lower byte of the program counter
Addressing Modes
Examples of the different addressing modes are discussed in
this section and example code is given.
Source Immediate
The result of an instruction using this addressing mode is
placed in the A register, the F register, the SP register, or the
X register, which is specified as part of the instruction opcode.
Operand 1 is an immediate value that serves as a source for
the instruction. Arithmetic instructions require two sources.
Instructions using this addressing mode are two bytes in
length.
Table 9. Source Immediate
Opcode
Instruction
Operand 1
Immediate Value
Examples
ADD A, 7 ;In this case, the immediate value
;of 7 is added with the Accumulator,
;and the result is placed in the
;Accumulator.
MOV X, 8 ;In this case, the immediate value
;of 8 is moved to the X register.
AND F, 9 ;In this case, the immediate value
;of 9 is logically ANDed with the F
;register and the result is placed
;in the F register.
Source Direct
The result of an instruction using this addressing mode is
placed in either the A register or the X register, which is
specified as part of the instruction opcode. Operand 1 is an
address that points to a location in either the RAM memory
space or the register space that is the source for the
instruction. Arithmetic instructions require two sources; the
second source is the A register or X register specified in the
opcode. Instructions using this addressing mode are two bytes
in length.
Table 10.Source Direct
Opcode
Instruction
Operand 1
Source Address
Examples
ADD A, [7]
;In this case, the value in
;the RAM memory location at
;address 7 is added with the
;Accumulator, and the result
;is placed in the Accumulator.
MOV X, REG[8] ;In this case, the value in
;the register space at address
;8 is moved to the X register.
Source Indexed
The result of an instruction using this addressing mode is
placed in either the A register or the X register, which is
Document #: 001-07552 Rev. *B
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