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PDF 74FCT138 Data sheet ( Hoja de datos )
| Número de pieza | 74FCT138 | |
| Descripción | IDT74FCT138 | |
| Fabricantes | IDT | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74FCT138 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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®
Integrated Device Technology, Inc.
FAST CMOS
1-OF-8 DECODER
WITH ENABLE
IDT54/74FCT138
IDT54/74FCT138A
IDT54/74FCT138C
FEATURES:
• IDT54/74FCT138 equivalent to FAST™ speed
• IDT54/74FCT138A 35% faster than FAST
• IDT54/74FCT138C 40% faster than FAST
• Equivalent to FAST speeds output drive over full tem-
perature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5µA max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing # 5962-87654 is listed on this
function. Refer to section 2.
DESCRIPTION:
The IDT54/74FCT138/A/C are 1-of-8 decoders built using
an advanced dual metal CMOS technology. The IDT54/
74FCT138/A/C accept three binary weighted inputs (A0, A1,
A2) and, when enabled, provide eight mutually exclusive
active LOW outputs (O 0 - O 7). The IDT54/74FCT138/A/C
feature three enable inputs, two active LOW (E 1, E 2) and one
active HIGH (E3). All outputs will be HIGH unless E 1 and E 2
are LOW and E3 is HIGH. This multiple enable function allows
easy parallel expansion of the device to a 1-of-32 (5 lines to
32 lines) decoder with just four IDT54/74FCT138/A/C devices
and one inverter.
FUNCTIONAL BLOCK DIAGRAM
A2 A1
A0
E1 E2 E3
PIN CONFIGURATIONS
A0
A1
A2
E1
E2
E3
O7
GND
1 16
2 15
3 P16-1, 14
4
D16-1,
SO16-1
13
5 & 12
6 E16-1 11
7 10
89
Vcc
O0
O1
O2
O3
O4
O5
O6
DIP/SOIC/CERPACK
TOP VIEW
O7 O6 O5 O4 O3 O2 O1 O0
2581 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.3
INDEX
3 2 20 19
A2 4
1 18 O1
E1 5
17 O2
NC 6 L20-2 16 NC
E2 7
15 O3
E3 8
14 O4
9 10 11 12 13
2581 drw 01
LCC
TOP VIEW
MAY 1992
DSC-4625/3
1
1 page  
IDT54/74FCT138/A/C
FAST CMOS 1-OF-8 DECODER-WITH ENABLE
wwwT.DEaStaTShCeeItR4UC.coUmITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC 7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500Ω
50pF
500Ω
RT CL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Test
Open
DEFINITIONS:
2581 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t SU
t SU
tH
t REM
tH
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
1.5V
tW
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
t PLH
t PHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
t PZL
SWITCH
CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
DISABLE
tPLZ
3V
1.5V
0V
3.5V
t PHZ
0.3V V OL
0.3V V OH
0V
NOTES
2581 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.3 5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74FCT138.PDF ] | |
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