PDF 74LVC1T45 Data sheet ( Hoja de datos )

Número de pieza	74LVC1T45
Descripción	Dual Supply Translating Transceiver
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com 74LVC1T45; 74LVCH1T45 Dual supply translating transceiver; 3-state Rev. 01 — 11 May 2009 Product data sheet 1. General description The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs that enables bidirectional level translation. They feature one data input-output port (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A. The devices are fully speciﬁed for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backﬂow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH1T45 holds unused or ﬂoating data inputs at a valid logic level. 2. Features I Wide supply voltage range: N VCC(A): 1.2 V to 5.5 V N VCC(B): 1.2 V to 5.5 V I High noise immunity I Complies with JEDEC standards: N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8C (2.7 V to 3.6 V) N JESD36 (4.5 V to 5.5 V) I ESD protection: N HBM JESD22-A114E Class 3A exceeds 4000 V N CDM JESD22-C101C exceeds 1000 V I Maximum data rates: N 420 Mbps (3.3 V to 5.0 V translation) N 210 Mbps (translate to 3.3 V)) N 140 Mbps (translate to 2.5 V) N 75 Mbps (translate to 1.8 V) N 60 Mbps (translate to 1.5 V) I Suspend mode 1 page www.DNatXaSPheSete4Um.coicmonductors 74LVC1T45; 74LVCH1T45 Dual supply translating transceiver; 3-state Table 6. Symbol VO Tamb ∆t/∆V Recommended operating conditions …continued Parameter Conditions output voltage Active mode Suspend or 3-state mode ambient temperature input transition rise and fall rate VCCI = 1.2 V to 5.5 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. 10. Static characteristics Min [1] 0 0 −40 [2] - Max VCCO 5.5 +125 5 Unit V V °C ns/V Table 7. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VOH HIGH-level output voltage VI = VIH or VIL IO = −3 mA; VCCO = 1.2 V [1] - VOL II IBHL IBHH IBHLO LOW-level output voltage input leakage current bus hold LOW current bus hold HIGH current bus hold LOW overdrive current VI = VIH or VIL IO = 3 mA; VCCO = 1.2 V DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V A or B port; VI = 0.42 V; VCCI = 1.2 V A or B port; VI = 0.78 V; VCCI = 1.2 V A or B port; VCCI = 1.2 V [1] - [2] - [2] - [2] - [2][3] - IBHHO bus hold HIGH overdrive A or B port; VCCI = 1.2 V current [2][3] - IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V [1] - IOFF power-off leakage current A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V - B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V - CI input capacitance DIR input; VI = 0 V or 5.5 V; VCC(A) = VCC(B) = 5.5 V - CI/O input/output capacitance A and B port; suspend mode; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - Typ 1.09 0.07 - 19 −19 19 −19 - - - 2.2 6.0 Max Unit -V -V ±1 µA - µA - µA - µA - µA ±1 µA ±1 µA ±1 µA - pF - pF [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. 74LVC_LVCH1T45_1 Product data sheet Rev. 01 — 11 May 2009 © NXP B.V. 2009. All rights reserved. 5 of 30 5 Page www.DNatXaSPheSete4Um.coicmonductors 74LVC1T45; 74LVCH1T45 Dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max tPZH OFF-state to HIGH DIR to A [1] - 35.2 - 33.7 - 25.2 - 23.9 - 21.8 ns propagation delay DIR to B [1] - 29.6 - 28.2 - 19.8 - 17.7 - 17.3 ns tPZL OFF-state to LOW DIR to A [1] - 39.4 - 36.2 - 24.4 - 22.9 - 20.4 ns propagation delay DIR to B [1] - 34.4 - 31.4 - 25.6 - 24.2 - 24.1 ns VCC(A) = 2.3 V to 2.7 V tPLH LOW to HIGH propagation delay A to B B to A 2.3 17.9 2.3 16.0 1.5 8.5 1.3 6.2 1.1 4.8 ns 2.0 13.5 2.2 9.3 1.5 8.5 1.4 8.0 1.0 7.5 ns tPHL HIGH to LOW A to B propagation delay B to A 2.3 15.8 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 ns 1.8 11.8 1.9 8.5 1.4 7.5 1.3 7.0 0.9 6.2 ns tPHZ HIGH to OFF-state DIR to A propagation delay DIR to B 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 ns 3.0 22.5 3.0 21.4 2.5 11.0 2.8 9.3 2.3 6.9 ns tPLZ LOW to OFF-state DIR to A propagation delay DIR to B 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 ns 2.3 14.6 2.5 13.2 2.0 9.0 2.5 8.4 1.8 5.3 ns tPZH OFF-state to HIGH DIR to A [1] - 28.1 - 22.5 - 17.5 - 16.4 - 12.8 ns propagation delay DIR to B [1] - 23.7 - 21.8 - 14.3 - 12.0 - 10.6 ns tPZL OFF-state to LOW DIR to A [1] - 34.3 - 29.9 - 18.5 - 16.3 - 13.1 ns propagation delay DIR to B [1] - 23.9 - 21.0 - 15.6 - 13.5 - 12.7 ns VCC(A) = 3.0 V to 3.6 V tPLH LOW to HIGH propagation delay A to B B to A 2.3 17.1 2.1 15.5 1.4 8.0 0.8 5.6 0.7 4.4 ns 1.7 11.8 1.7 7.2 1.3 6.2 0.7 5.6 0.6 5.4 ns tPHL HIGH to LOW A to B propagation delay B to A 2.2 15.6 2.0 12.6 1.3 7.0 0.8 5.0 0.7 4.0 ns 1.7 10.9 1.8 7.1 1.3 5.4 0.8 5.0 0.7 4.5 ns tPHZ HIGH to OFF-state DIR to A propagation delay DIR to B 2.3 7.3 2.3 7.3 2.3 7.3 2.3 7.3 2.7 7.3 ns 2.9 18.0 2.9 16.5 2.3 10.1 2.7 8.6 2.2 6.3 ns tPLZ LOW to OFF-state DIR to A propagation delay DIR to B 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 ns 2.3 13.6 2.4 12.5 1.9 7.8 2.3 7.1 1.7 4.9 ns tPZH OFF-state to HIGH DIR to A [1] - 25.4 - 19.7 - 14.0 - 12.7 - 10.3 ns propagation delay DIR to B [1] - 22.7 - 21.1 - 13.6 - 11.2 - 10.0 ns tPZL OFF-state to LOW DIR to A [1] - 28.9 - 23.6 - 15.5 - 13.6 - 10.8 ns propagation delay DIR to B [1] - 22.9 - 19.9 - 14.3 - 12.3 - 11.3 ns VCC(A) = 4.5 V to 5.5 V tPLH LOW to HIGH propagation delay A to B B to A 2.2 16.6 1.9 15.1 1.0 7.5 0.7 5.4 0.5 3.9 ns 1.6 10.5 1.4 6.8 1.0 4.8 0.7 4.4 0.5 3.9 ns tPHL HIGH to LOW A to B propagation delay B to A 2.3 15.3 1.8 12.2 1.0 6.2 0.7 4.5 0.5 3.5 ns 1.7 10.8 1.7 7.0 0.9 4.6 0.7 4.0 0.5 3.5 ns tPHZ HIGH to OFF-state DIR to A propagation delay DIR to B 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 ns 2.9 17.3 2.9 16.1 2.3 9.7 2.7 8.0 2.5 5.7 ns 74LVC_LVCH1T45_1 Product data sheet Rev. 01 — 11 May 2009 © NXP B.V. 2009. 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