UM10334 Datasheet PDF - NXP Semiconductors
Part Number | UM10334 | |
Description | User Manual | |
Manufacturers | NXP Semiconductors | |
Logo | ||
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UM10334
P89LPC9301/931A1 User manual
Rev. 01 — 9 April 2009
User manual
Document information
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Keywords
P89LPC9301/931A1
Abstract
Technical information for the P89LPC9301/931A1 device
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NXP Semiconductors
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UM10334
P89LPC9301/931A1 User manual
Table 1. Pin description …continued
Symbol
Pin Type Description
TSSOP28
P1.5/RST 6 I P1.5 — Port 1 bit 5 (input only).
I RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
P1.6
5 I/O P1.6 — Port 1 bit 6. High current source.
P1.7
4 I/O P1.7 — Port 1 bit 7. High current source.
P2.0 to P2.7
I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
4.1 “Port configurations” for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0
1 I/O P2.0 — Port 2 bit 0.
P2.1
2 I/O P2.1 — Port 2 bit 1.
P2.2/MOSI 13 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input.
P2.3/MISO 14 I/O P2.3 — Port 2 bit 3.
I/O MISO — When configured as master, this pin is input, when configured as slave,
this pin is output.
P2.4/SS
15 I/O P2.4 — Port 2 bit 4.
I SS — SPI Slave select.
P2.5/SPICLK
16
I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6
27 I/O P2.6 — Port 2 bit 6.
P2.7
28 I/O P2.7 — Port 2 bit 7.
P3.0 to P3.1
I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
4.1 “Port configurations” for details.
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
9
I/O P3.0 — Port 3 bit 0.
O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration.
O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the RTC/system timer.
UM10334_1
User manual
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
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