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PDF STP13NK50Z Data sheet ( Hoja de datos )
| Número de pieza | STP13NK50Z | |
| Descripción | Power MOSFETs | |
| Fabricantes | ST Microelectronics | |
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STF13NK50Z
STP13NK50Z - STW13NK50Z
N-channel 500V - 0.40Ω - 11A TO-220/TO-220FP/TO-247
Zener-protected SuperMESHTM Power MOSFET
Features
Type
STF13NK50Z
STP13NK50Z
STW13NK50Z
VDSS
500 V
500 V
500 V
RDS(on) ID
<0.48 Ω 11 A
<0.48 Ω 11 A
<0.48 Ω 11 A
Pw
30 W
140 W
140 W
■ Extremely high dv/dt capability
■ 100% avalanche tested
■ Gate charge minimized
■ Very low intrinsic capacitances
■ Very good manufacturing repeatability
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs.
Applications
■ Switching application
3
2
1
TO-220
3
2
1
TO-220FP
TO-247
Figure 1. Internal schematic diagram
Table 1. Device summary
Order code
STF13NK50Z
STP13NK50Z
STW13NK50Z
Marking
F13NK50Z
P13NK50Z
W13NK50Z
Package
TO-220FP
TO-220
TO-247
August 2007
Rev 1
Packaging
Tube
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2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 6. On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
IDSS
Zero gate voltage drain
current (VGS = 0)
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VDS = 0)
Gate threshold voltage
Static drain-source on
resistance
ID = 1 mA, VGS= 0
VDS = Max rating,
VDS = Max rating,
TC =125 °C
VGS = ± 20 V
VDS= VGS, ID = 100 µA
VGS= 10 V, ID= 6.5 A
Min. Typ. Max. Unit
500 V
1 µA
50 µA
±10 µA
3 3.75 4.5 V
0.4 0.48 Ω
Table 7. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1) Forward transconductance VDS =15 V, ID = 6.5 A
8.5 S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25 V, f=1 MHz,
VGS=0
1600
200
45
pF
pF
pF
Coss
(2)
eq .
Equivalent output
capacitance
VGS=0, VDS =0 V to 400 V
50
pF
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=400 V, ID = 6.5 A
VGS =10 V
(see Figure 20)
47 nC
9 nC
28 nC
Rg Intrinsic gate resistance
f= 1 MHz open drain
2.3 Ω
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
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4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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| PDF Descargar | [ Datasheet STP13NK50Z.PDF ] | |
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