PDF MC74HC4017 Data sheet ( Hoja de datos )

Número de pieza	MC74HC4017
Descripción	DECADE COUNTER
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Decade Counterwww.DataSheet4U.com High–Performance Silicon–Gate CMOS The MC74HC4017 is identical in pinout to the standard CMOS MC14017B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4017 uses a five stage Johnson counter and decoding logic to provide high–speed operation. This device also has an active–high, as well as active–low clock input. • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2 to 6 V • Low Input Current: 1 µA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 176 FETs or 44 Equivalent Gates LOGIC DIAGRAM 14 CLOCK CLOCK 13 ENABLE RESET 15 3 Q0 2 Q1 4 Q2 7 Q3 10 Q4 1 Q5 5 Q6 6 Q7 9 Q8 11 Q9 DECADE OUTPUTS 12 CARRY OUT PIN 16 = VCC PIN 8 = GND MC74HC4017 16 1 N SUFFIX PLASTIC PACKAGE CASE 648–08 16 1 D SUFFIX SOIC PACKAGE CASE 751B–05 ORDERING INFORMATION MC74HCXXXXN MC74HCXXXXD Plastic SOIC PIN ASSIGNMENT Q5 1 Q1 2 16 VCC 15 RESET Q0 3 14 CLOCK Q2 4 Q6 5 13 CLOCK ENABLE 12 CARRY OUT Q7 6 Q3 7 11 Q9 10 Q4 GND 8 9 Q8 10/95 © Motorola, Inc. 1995 1 REV 6 1 page MC74HC4017 www.DataSheet4U.com tr CLOCK 90% 50% 10% tw 1/fmax 90% Q 50% 10% tPLH tTLH tf tPHL tTHL Figure 1. RESET Q1–Q9 Q0, CARRY OUT 50% tw tPHL 50% tPLH 50% Figure 3. CLOCK ENABLE tPHL CARRY OUT 50% 50% Figure 5. SWITCHING WAVEFORMS VCC CLOCK 50% GND tw tPLH CARRY OUT 50% VCC GND tPHL Figure 2. VCC GND VCC GND VCC GND tPLH CLOCK ENABLE Q tw 50% tPLH 50% Figure 4. VCC GND tPHL CLOCK ENABLE CLOCK VALID 50% tsu th 50% Figure 6. Q0 – Q9, CARRY OUT tTLH 90% 10% tTHL Figure 8. VCC GND VCC GND CLOCK RESET 50% trec 50% Figure 7. VCC GND VCC GND DEVICE UNDER TEST TEST POINT OUTPUT CL* * Includes all probe and jig capacitance Figure 9. Test Circuit High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA 5 Page

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